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(unknown [78.208.223.3]) by zproxy3.enst.fr (Postfix) with ESMTPSA id 5F5FBA0576; Sun, 24 Mar 2024 17:57:27 +0100 (CET) From: Arnaud Minier To: qemu-devel@nongnu.org Cc: Laurent Vivier , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-arm@nongnu.org, Paolo Bonzini , Alistair Francis , Arnaud Minier , Thomas Huth , =?UTF-8?q?In=C3=A8s=20Varhol?= , Samuel Tardieu , Peter Maydell Subject: [PATCH v2 4/6] hw/char/stm32l4x5_usart: Add options for serial parameters setting Date: Sun, 24 Mar 2024 17:55:44 +0100 Message-Id: <20240324165545.201908-5-arnaud.minier@telecom-paris.fr> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240324165545.201908-1-arnaud.minier@telecom-paris.fr> References: <20240324165545.201908-1-arnaud.minier@telecom-paris.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=137.194.2.222; envelope-from=arnaud.minier@telecom-paris.fr; helo=zproxy3.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add a function to change the settings of the serial connection. Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol --- hw/char/stm32l4x5_usart.c | 98 +++++++++++++++++++++++++++++++++++++++ hw/char/trace-events | 1 + 2 files changed, 99 insertions(+) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index ec8c2f6e63..b4d11dd826 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -267,6 +267,92 @@ static void usart_cancel_transmit(Stm32l4x5UsartBase= State *s) } } =20 +static void stm32l4x5_update_params(Stm32l4x5UsartBaseState *s) +{ + int speed, parity, data_bits, stop_bits; + uint32_t value, usart_div; + QEMUSerialSetParams ssp; + + /* Select the parity type */ + if (s->cr1 & R_CR1_PCE_MASK) { + if (s->cr1 & R_CR1_PS_MASK) { + parity =3D 'O'; + } else { + parity =3D 'E'; + } + } else { + parity =3D 'N'; + } + + /* Select the number of stop bits */ + switch (FIELD_EX32(s->cr2, CR2, STOP)) { + case 0: + stop_bits =3D 1; + break; + case 2: + stop_bits =3D 2; + break; + default: + qemu_log_mask(LOG_UNIMP, + "UNIMPLEMENTED: fractionnal stop bits; CR2[13:12] =3D %x", + FIELD_EX32(s->cr2, CR2, STOP)); + return; + } + + /* Select the length of the word */ + switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1,= M0)) { + case 0: + data_bits =3D 8; + break; + case 1: + data_bits =3D 9; + break; + case 2: + data_bits =3D 7; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "UNDEFINED: invalid word length, CR1.M =3D 0b11"); + return; + } + + /* Select the baud rate */ + value =3D FIELD_EX32(s->brr, BRR, BRR); + if (value < 16) { + qemu_log_mask(LOG_GUEST_ERROR, + "UNDEFINED: BRR lesser than 16: %u", value); + return; + } + + if (FIELD_EX32(s->cr1, CR1, OVER8) =3D=3D 0) { + /* + * Oversampling by 16 + * BRR =3D USARTDIV + */ + usart_div =3D value; + } else { + /* + * Oversampling by 8 + * - BRR[2:0] =3D USARTDIV[3:0] shifted 1 bit to the right. + * - BRR[3] must be kept cleared. + * - BRR[15:4] =3D USARTDIV[15:4] + * - The frequency is multiplied by 2 + */ + usart_div =3D ((value & 0xFFF0) | ((value & 0x0007) << 1)) / 2; + } + + speed =3D clock_get_hz(s->clk) / usart_div; + + ssp.speed =3D speed; + ssp.parity =3D parity; + ssp.data_bits =3D data_bits; + ssp.stop_bits =3D stop_bits; + + qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); + + trace_stm32l4x5_usart_update_params(speed, parity, data_bits, stop_b= its); +} + static void stm32l4x5_usart_base_reset_hold(Object *obj) { Stm32l4x5UsartBaseState *s =3D STM32L4X5_USART_BASE(obj); @@ -365,16 +451,19 @@ static void stm32l4x5_usart_base_write(void *opaque= , hwaddr addr, switch (addr) { case A_CR1: s->cr1 =3D value; + stm32l4x5_update_params(s); stm32l4x5_update_irq(s); return; case A_CR2: s->cr2 =3D value; + stm32l4x5_update_params(s); return; case A_CR3: s->cr3 =3D value; return; case A_BRR: s->brr =3D value; + stm32l4x5_update_params(s); return; case A_GTPR: s->gtpr =3D value; @@ -443,10 +532,19 @@ static void stm32l4x5_usart_base_init(Object *obj) s->clk =3D qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); } =20 +static int stm32l4x5_usart_base_post_load(void *opaque, int version_id) +{ + Stm32l4x5UsartBaseState *s =3D (Stm32l4x5UsartBaseState *)opaque; + + stm32l4x5_update_params(s); + return 0; +} + static const VMStateDescription vmstate_stm32l4x5_usart_base =3D { .name =3D TYPE_STM32L4X5_USART_BASE, .version_id =3D 1, .minimum_version_id =3D 1, + .post_load =3D stm32l4x5_usart_base_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), diff --git a/hw/char/trace-events b/hw/char/trace-events index f22f0ee2bc..8875758076 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -116,6 +116,7 @@ stm32l4x5_usart_irq_raised(uint32_t reg) "USART: IRQ = raised: 0x%08"PRIx32 stm32l4x5_usart_irq_lowered(void) "USART: IRQ lowered" stm32l4x5_usart_overrun_detected(uint8_t current, uint8_t received) "USA= RT: Overrun detected, RDR=3D'0x%x', received 0x%x" stm32l4x5_usart_receiver_not_enabled(uint8_t ue_bit, uint8_t re_bit) "US= ART: Receiver not enabled, UE=3D0x%x, RE=3D0x%x" +stm32l4x5_usart_update_params(int speed, uint8_t parity, int data, int s= top) "USART: speed: %d, parity: %c, data bits: %d, stop bits: %d" =20 # xen_console.c xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned in= t port, unsigned int limit) "idx %u ring_ref %u port %u limit %u" --=20 2.34.1