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Sat, 11 May 2024 15:04:10 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d878fsm1123875e87.206.2024.05.11.15.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 May 2024 15:04:09 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:07 +0300 Subject: [PATCH v4 1/9] dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240512-typec-fix-sm8250-v4-1-ad153c747a97@linaro.org> References: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> In-Reply-To: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2305; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Pl/YNaCowSJwtvM5CLxzriI2N0LVr+hVT798TnH3gks=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmP+tXp0Q5GwpORS+iXqTB5ajH8osXG5Ezc0mES IOnbKfLsZSJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj/rVwAKCRCLPIo+Aiko 1RZbB/9jfNSvkrAiw3FfSqlT7aAyrEiQRJI/7aZT73ThY08D9L8FFb8NDFAcOcZ3/+053LXmFG+ 7Q442pF4cmedrD8wYwP3gFja36hQ9tkKQM6yGvG0Hv5fZm9l1rhA2TPWYZZEeGv+1K5mKmY/L96 e2YRvo1w4VJYmnKtThuFlqakeBXsRjIc3xGq928b+yjpsl6yR1hmMsP6yuYJU2b19mzlaHbMqfQ SmM3zfh1gDpOF69ODUM/GRk3Nj2Vs5eXlQ/9o6Sf/WPLsZfTovepUjeKXwDTzUzOvHT6tJP/VmG vjvVve7M2ka3tZg4hBSZ/drWzqx4onBz/mCErRXDBej7DjMt X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On the affected Qualcomm platforms the display clock controller has additional DP input clocks, describe them in DT schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 59cc88a52f6b..5831579b572e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -27,6 +27,7 @@ properties: - qcom,sm8350-dispcc clocks: + minItems: 7 items: - description: Board XO source - description: Byte clock from DSI PHY0 @@ -35,8 +36,15 @@ properties: - description: Pixel clock from DSI PHY1 - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY + - description: Link clock from eDP PHY + - description: VCO DIV clock from eDP PHY + - description: Link clock from DP1 PHY + - description: VCO DIV clock from DP1 PHY + - description: Link clock from DP2 PHY + - description: VCO DIV clock from DP2 PHY clock-names: + minItems: 7 items: - const: bi_tcxo - const: dsi0_phy_pll_out_byteclk @@ -45,6 +53,12 @@ properties: - const: dsi1_phy_pll_out_dsiclk - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk + - const: edp_phy_pll_link_clk + - const: edp_phy_pll_vco_div_clk + - const: dptx1_phy_pll_link_clk + - const: dptx1_phy_pll_vco_div_clk + - const: dptx2_phy_pll_link_clk + - const: dptx2_phy_pll_vco_div_clk '#clock-cells': const: 1 @@ -68,6 +82,20 @@ properties: A phandle to an OPP node describing required MMCX performance point. maxItems: 1 +allOf: + - if: + not: + properties: + compatible: + contains: + const: qcom,sc8180x-dispcc + then: + properties: + clocks: + maxItems: 7 + clock-names: + maxItems: 7 + required: - compatible - reg -- 2.39.2