From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 09 Jan 2019 22:37:35 -0000 Received: from mx1.redhat.com ([209.132.183.28]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1ghMTd-00066N-Hb for speck@linutronix.de; Wed, 09 Jan 2019 23:37:34 +0100 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5972858E38 for ; Wed, 9 Jan 2019 22:37:27 +0000 (UTC) Received: from [10.36.112.23] (ovpn-112-23.ams2.redhat.com [10.36.112.23]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5A191608DA for ; Wed, 9 Jan 2019 22:37:25 +0000 (UTC) Subject: [MODERATED] Re: qemu patch for mb_clear References: <20181221003101.GA32181@tassilo.jf.intel.com> <20190109170919.GU23427@char.us.oracle.com> <2a833765-3d5a-3664-dd5e-3a256a29ff4b@redhat.com> <20190109215550.GX6118@tassilo.jf.intel.com> From: Paolo Bonzini Message-ID: <20254dbf-a01a-97c4-ac76-c75714b48d05@redhat.com> Date: Wed, 9 Jan 2019 23:37:23 +0100 MIME-Version: 1.0 In-Reply-To: <20190109215550.GX6118@tassilo.jf.intel.com> Content-Type: multipart/mixed; boundary="VDWFBk70UfxatE6grUhODchlcujqtaCjo"; protected-headers="v1" To: speck@linutronix.de List-ID: This is an OpenPGP/MIME encrypted message (RFC 4880 and 3156) --VDWFBk70UfxatE6grUhODchlcujqtaCjo Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: quoted-printable On 09/01/19 22:55, speck for Andi Kleen wrote: >>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >>>> index 677a3bd5fb25..77a1149e4bb3 100644 >>>> --- a/target/i386/cpu.c >>>> +++ b/target/i386/cpu.c >>>> @@ -1038,7 +1038,7 @@ static FeatureWordInfo feature_word_info[FEATU= RE_WORDS] =3D { >>>> .feat_names =3D { >>>> NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", >>>> NULL, NULL, NULL, NULL, >>>> - NULL, NULL, NULL, NULL, >>>> + NULL, NULL, "mbclear", NULL, >>>> NULL, NULL, NULL, NULL, >>>> NULL, NULL, "pconfig", NULL, >>>> NULL, NULL, NULL, NULL, >> >> Are there any CPU families which will all have it (e.g. IceLake server= , >> Cascade Lake?). Prerelease/prototype silicon does not count. >=20 > All the past ones which get the VERW microcode update > (somewhere between Nehalem and Skylake) >=20 > Future systems which don't have/need VERW won't have it in fact Then Reviewed-by: Paolo Bonzini Thanks! Paolo --VDWFBk70UfxatE6grUhODchlcujqtaCjo--