From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755272AbbBTRuW (ORCPT ); Fri, 20 Feb 2015 12:50:22 -0500 Received: from cantor2.suse.de ([195.135.220.15]:53694 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754214AbbBTRuV convert rfc822-to-8bit (ORCPT ); Fri, 20 Feb 2015 12:50:21 -0500 Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (1.0) Subject: Re: [Qemu-devel] [RFC PATCH v2 04/15] cpu-model/s390: Introduce S390 CPU models From: Alexander Graf X-Mailer: iPhone Mail (12B411) In-Reply-To: <20150220183748.45b32e11@bee> Date: Fri, 20 Feb 2015 18:50:20 +0100 Cc: "qemu-devel@nongnu.org" , "kvm@vger.kernel.org" , "linux-s390@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Gleb Natapov , Christian Borntraeger , "Jason J. Herne" , Cornelia Huck , Paolo Bonzini , Andreas Faerber , Richard Henderson Content-Transfer-Encoding: 8BIT Message-Id: <2049D8E0-FE03-4E84-94D0-E23B695BC865@suse.de> References: <1424183053-4310-1-git-send-email-mimu@linux.vnet.ibm.com> <1424183053-4310-5-git-send-email-mimu@linux.vnet.ibm.com> <54E73C8F.7000202@suse.de> <20150220160046.4743acc8@bee> <89E3550E-9E2B-4D95-A809-B7C64EBCD7C5@suse.de> <20150220164944.4eb4eeb3@bee> <54E76790.1030700@suse.de> <20150220183748.45b32e11@bee> To: Michael Mueller Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Am 20.02.2015 um 18:37 schrieb Michael Mueller : > > On Fri, 20 Feb 2015 17:57:52 +0100 > Alexander Graf wrote: > >> Because all CPUs we have in our list only expose 128 bits? > > Here a STFLE result on a EC12 GA2, already more than 128 bits... Is that model on the list? If that model has 3 elements, yes, the array should span 3. I hope it's in the list. Every model wecare about should be, no? > > [mimu@p57lp59 s390xfac]$ ./s390xfac -b > fac[0] = 0xfbfffffbfcfff840 > fac[1] = 0xffde000000000000 > fac[2] = 0x1800000000000000 >> >>> I want to have this independent from a future machine of the z/Arch. The kernel stores the >>> full facility set, KVM does and there is no good reason for QEMU not to do. If other >>> accelerators decide to just implement 64 or 128 bits of facilities that's ok... >> >> So you want to support CPUs that are not part of the list? > > The architecture at least defines more than 2 or 3. Do you want me to limit it to an arbitrary > size?. Only in QEMU or also in the KVM interface? Only internally in QEMU. The kvm interface should definitely be as big as the spec allows! Alex > > Thanks > Michael > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YOriZ-0002rg-Hh for qemu-devel@nongnu.org; Fri, 20 Feb 2015 12:50:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YOriW-0006lT-KZ for qemu-devel@nongnu.org; Fri, 20 Feb 2015 12:50:23 -0500 Received: from cantor2.suse.de ([195.135.220.15]:48423 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YOriW-0006l3-Ei for qemu-devel@nongnu.org; Fri, 20 Feb 2015 12:50:20 -0500 Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (1.0) From: Alexander Graf In-Reply-To: <20150220183748.45b32e11@bee> Date: Fri, 20 Feb 2015 18:50:20 +0100 Content-Transfer-Encoding: quoted-printable Message-Id: <2049D8E0-FE03-4E84-94D0-E23B695BC865@suse.de> References: <1424183053-4310-1-git-send-email-mimu@linux.vnet.ibm.com> <1424183053-4310-5-git-send-email-mimu@linux.vnet.ibm.com> <54E73C8F.7000202@suse.de> <20150220160046.4743acc8@bee> <89E3550E-9E2B-4D95-A809-B7C64EBCD7C5@suse.de> <20150220164944.4eb4eeb3@bee> <54E76790.1030700@suse.de> <20150220183748.45b32e11@bee> Subject: Re: [Qemu-devel] [RFC PATCH v2 04/15] cpu-model/s390: Introduce S390 CPU models List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Mueller Cc: "linux-s390@vger.kernel.org" , "kvm@vger.kernel.org" , Gleb Natapov , "qemu-devel@nongnu.org" , "linux-kernel@vger.kernel.org" , Christian Borntraeger , "Jason J. Herne" , Cornelia Huck , Paolo Bonzini , Andreas Faerber , Richard Henderson > Am 20.02.2015 um 18:37 schrieb Michael Mueller : >=20 > On Fri, 20 Feb 2015 17:57:52 +0100 > Alexander Graf wrote: >=20 >> Because all CPUs we have in our list only expose 128 bits? >=20 > Here a STFLE result on a EC12 GA2, already more than 128 bits... Is that m= odel on the list? If that model has 3 elements, yes, the array should span 3. I hope it's in the list. Every model wecare about should be, no? >=20 > [mimu@p57lp59 s390xfac]$ ./s390xfac -b > fac[0] =3D 0xfbfffffbfcfff840 > fac[1] =3D 0xffde000000000000 > fac[2] =3D 0x1800000000000000 >>=20 >>> I want to have this independent from a future machine of the z/Arch. The= kernel stores the >>> full facility set, KVM does and there is no good reason for QEMU not to d= o. If other >>> accelerators decide to just implement 64 or 128 bits of facilities that'= s ok... =20 >>=20 >> So you want to support CPUs that are not part of the list? >=20 > The architecture at least defines more than 2 or 3. Do you want me to limi= t it to an arbitrary > size?. Only in QEMU or also in the KVM interface? Only internally in QEMU. The kvm interface should definitely be as big as th= e spec allows! Alex >=20 > Thanks > Michael >=20