From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752432AbdDEEWi (ORCPT ); Wed, 5 Apr 2017 00:22:38 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:51522 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751098AbdDEEWg (ORCPT ); Wed, 5 Apr 2017 00:22:36 -0400 Subject: Re: [PATCH v6 01/11] powerpc/powernv: Data structure and macros definitions To: Daniel Axtens , mpe@ellerman.id.au References: <1491231308-15282-1-git-send-email-maddy@linux.vnet.ibm.com> <1491231308-15282-2-git-send-email-maddy@linux.vnet.ibm.com> <87h925kkn1.fsf@possimpible.ozlabs.ibm.com> Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, ego@linux.vnet.ibm.com, bsingharora@gmail.com, benh@kernel.crashing.org, paulus@samba.org, anton@samba.org, sukadev@linux.vnet.ibm.com, mikey@neuling.org, stewart@linux.vnet.ibm.com, eranian@google.com, Hemant Kumar , Anju T Sudhakar From: Madhavan Srinivasan Date: Wed, 5 Apr 2017 09:52:26 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <87h925kkn1.fsf@possimpible.ozlabs.ibm.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-MML: disable x-cbid: 17040504-0012-0000-0000-000003DC4AE3 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17040504-0013-0000-0000-00001B6259F1 Message-Id: <204d2af0-aa83-19c3-7a1a-cf1b7215ac4a@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-04-05_04:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1704050039 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 04 April 2017 07:18 AM, Daniel Axtens wrote: > Hi, > >> +#define IMC_MAX_CHIPS 32 >> +#define IMC_MAX_PMUS 32 >> +#define IMC_MAX_PMU_NAME_LEN 256 > I've noticed this is used as both the maximum length for event names and > event value strings. Would another name suit better? This is used in the value string length comparison also. So yes, will change the name to suit better. Thanks for review Maddy > >> + >> +#define IMC_NEST_MAX_PAGES 16 >> + >> +#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters" >> +#define IMC_DTB_NEST_COMPAT "ibm,imc-counters-nest" >> + >> +/* >> + * Structure to hold per chip specific memory address >> + * information for nest pmus. Nest Counter data are exported >> + * in per-chip reserved memory region by the PORE Engine. >> + */ >> +struct perchip_nest_info { >> + u32 chip_id; >> + u64 pbase; >> + u64 vbase[IMC_NEST_MAX_PAGES]; >> + u64 size; >> +}; >> + >> +/* >> + * Place holder for nest pmu events and values. >> + */ >> +struct imc_events { >> + char *ev_name; >> + char *ev_value; >> +}; >> + >> +/* >> + * Device tree parser code detects IMC pmu support and >> + * registers new IMC pmus. This structure will >> + * hold the pmu functions and attrs for each imc pmu and >> + * will be referenced at the time of pmu registration. >> + */ >> +struct imc_pmu { >> + struct pmu pmu; >> + int domain; >> + const struct attribute_group *attr_groups[4]; >> +}; >> + >> +/* >> + * Domains for IMC PMUs >> + */ >> +#define IMC_DOMAIN_NEST 1 >> +#define IMC_DOMAIN_UNKNOWN -1 >> + >> +#endif /* PPC_POWERNV_IMC_PMU_DEF_H */ >> -- >> 2.7.4