From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=FROM_EXCESS_BASE64, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCCA5C43142 for ; Thu, 28 Jun 2018 05:16:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8554D26CD9 for ; Thu, 28 Jun 2018 05:16:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8554D26CD9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=siol.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752888AbeF1FQu convert rfc822-to-8bit (ORCPT ); Thu, 28 Jun 2018 01:16:50 -0400 Received: from mailoutvs35.siol.net ([185.57.226.226]:48603 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751466AbeF1FQs (ORCPT ); Thu, 28 Jun 2018 01:16:48 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id D438052060B; Thu, 28 Jun 2018 07:16:45 +0200 (CEST) X-Virus-Scanned: amavisd-new at psrvmta10.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta10.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id aTn74bYr9D70; Thu, 28 Jun 2018 07:16:44 +0200 (CEST) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 6BDBB5201BF; Thu, 28 Jun 2018 07:16:44 +0200 (CEST) Received: from jernej-laptop.localnet (unknown [194.152.15.144]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPA id 1EA8252060B; Thu, 28 Jun 2018 07:16:43 +0200 (CEST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Chen-Yu Tsai Cc: Maxime Ripard , Rob Herring , David Airlie , Gustavo Padovan , Maarten Lankhorst , Sean Paul , Mark Rutland , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk , linux-sunxi Subject: Re: [PATCH v3 23/24] ARM: dts: sun8i: r40: Add HDMI pipeline Date: Thu, 28 Jun 2018 07:15:18 +0200 Message-ID: <21259128.K3MyN3b6Bq@jernej-laptop> In-Reply-To: References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-24-jernej.skrabec@siol.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dne četrtek, 28. junij 2018 ob 04:50:09 CEST je Chen-Yu Tsai napisal(a): > On Mon, Jun 25, 2018 at 8:03 PM, Jernej Skrabec wrote: > > Add all entries needed for HDMI to function properly. > > > > Since R40 has highly configurable pipeline, both mixers and both TCON > > TVs are added. Board specific DT should then connect them together > > trough TCON TOP muxers to best fit the purpose of the board. > > > > Signed-off-by: Jernej Skrabec > > --- > > > > arch/arm/boot/dts/sun8i-r40.dtsi | 269 +++++++++++++++++++++++++++++++ > > 1 file changed, 269 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi > > b/arch/arm/boot/dts/sun8i-r40.dtsi index 173dcc1652d2..a2a75fb04caf > > 100644 > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi > > @@ -42,8 +42,11 @@ > > > > */ > > > > #include > > > > +#include > > > > #include > > > > +#include Maxime, above line breaks compilation for build robot, sorry. > > > > #include > > > > +#include > > > > / { > > > > #address-cells = <1>; > > > > @@ -99,12 +102,76 @@ > > > > }; > > > > }; > > > > + de: display-engine { > > + compatible = "allwinner,sun8i-r40-display-engine", > > + "allwinner,sun8i-h3-display-engine"; > > Given that the display pipeline looks different, they should not be > compatible. Ok. > > > + allwinner,pipelines = <&mixer0>, <&mixer1>; > > + status = "disabled"; > > + }; > > + > > > > soc { > > > > compatible = "simple-bus"; > > #address-cells = <1>; > > #size-cells = <1>; > > ranges; > > > > + display_clocks: clock@1000000 { > > + compatible = "allwinner,sun8i-r40-de2-clk", > > + "allwinner,sun8i-h3-de2-clk"; > > + reg = <0x01000000 0x100000>; > > + clocks = <&ccu CLK_DE>, > > + <&ccu CLK_BUS_DE>; > > + clock-names = "mod", > > + "bus"; > > + resets = <&ccu RST_BUS_DE>; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + }; > > + > > + mixer0: mixer@1100000 { > > + compatible = "allwinner,sun8i-r40-de2-mixer-0"; > > + reg = <0x01100000 0x100000>; > > + clocks = <&display_clocks CLK_BUS_MIXER0>, > > + <&display_clocks CLK_MIXER0>; > > + clock-names = "bus", > > + "mod"; > > + resets = <&display_clocks RST_MIXER0>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mixer0_out: port@1 { > > + reg = <1>; > > + mixer0_out_tcon_top: endpoint { > > + remote-endpoint = > > <&tcon_top_mixer0_in_mixer0>; + }; > > + }; > > + }; > > + }; > > + > > + mixer1: mixer@1200000 { > > + compatible = "allwinner,sun8i-r40-de2-mixer-1"; > > + reg = <0x01200000 0x100000>; > > + clocks = <&display_clocks CLK_BUS_MIXER1>, > > + <&display_clocks CLK_MIXER1>; > > + clock-names = "bus", > > + "mod"; > > + resets = <&display_clocks RST_WB>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mixer1_out: port@1 { > > + reg = <1>; > > + mixer1_out_tcon_top: endpoint { > > + remote-endpoint = > > <&tcon_top_mixer1_in_mixer1>; + }; > > + }; > > + }; > > + }; > > + > > > > nmi_intc: interrupt-controller@1c00030 { > > > > compatible = "allwinner,sun7i-a20-sc-nmi"; > > interrupt-controller; > > > > @@ -451,6 +518,163 @@ > > > > #size-cells = <0>; > > > > }; > > > > + tcon_top: tcon-top@1c70000 { > > + compatible = "allwinner,sun8i-r40-tcon-top"; > > + reg = <0x01c70000 0x1000>; > > + clocks = <&ccu CLK_BUS_TCON_TOP>, > > + <&ccu CLK_TCON_TV0>, > > + <&ccu CLK_TVE0>, > > + <&ccu CLK_TCON_TV1>, > > + <&ccu CLK_TVE1>, > > + <&ccu CLK_DSI_DPHY>; > > + clock-names = "bus", > > + "tcon-tv0", > > + "tve0", > > + "tcon-tv1", > > + "tve1", > > + "dsi"; > > + clock-output-names = "tcon-top-tv0", > > + "tcon-top-tv1", > > + "tcon-top-dsi"; > > + resets = <&ccu RST_BUS_TCON_TOP>; > > + #clock-cells = <1>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + tcon_top_mixer0_in: port@0 { > > + reg = <0>; > > + > > + tcon_top_mixer0_in_mixer0: > > endpoint { + > > remote-endpoint = <&mixer0_out_tcon_top>; + > > }; > > + }; > > + > > + tcon_top_mixer0_out: port@1 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <1>; > > + > > + tcon_top_mixer0_out_tcon_lcd0: > > endpoint@0 { + reg = <0>; > > + }; > > + > > + tcon_top_mixer0_out_tcon_lcd1: > > endpoint@1 { + reg = <1>; > > + }; > > + > > + tcon_top_mixer0_out_tcon_tv0: > > endpoint@2 { + reg = <2>; > > + }; > > + > > + tcon_top_mixer0_out_tcon_tv1: > > endpoint@3 { + reg = <3>; > > + }; > > + }; > > + > > + tcon_top_mixer1_in: port@2 { > > + reg = <2>; > > + > > + tcon_top_mixer1_in_mixer1: > > endpoint { + > > remote-endpoint = <&mixer1_out_tcon_top>; + > > }; > > + }; > > + > > + tcon_top_mixer1_out: port@3 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <3>; > > + > > + tcon_top_mixer1_out_tcon_lcd0: > > endpoint@0 { + reg = <0>; > > + }; > > + > > + tcon_top_mixer1_out_tcon_lcd1: > > endpoint@1 { + reg = <1>; > > + }; > > + > > + tcon_top_mixer1_out_tcon_tv0: > > endpoint@2 { + reg = <2>; > > + }; > > + > > + tcon_top_mixer1_out_tcon_tv1: > > endpoint@3 { + reg = <3>; > > + }; > > + }; > > + > > + tcon_top_hdmi_in: port@4 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <4>; > > + > > + tcon_top_hdmi_in_tcon_tv0: > > endpoint@0 { + reg = <0>; > > + }; > > + > > + tcon_top_hdmi_in_tcon_tv1: > > endpoint@1 { + reg = <1>; > > + }; > > + }; > > + > > + tcon_top_hdmi_out: port@5 { > > + reg = <5>; > > + > > + tcon_top_hdmi_out_hdmi: endpoint { > > + remote-endpoint = > > <&hdmi_in_tcon_top>; + }; > > + }; > > + }; > > + }; > > + > > + tcon_tv0: lcd-controller@1c73000 { > > + compatible = "allwinner,sun8i-r40-tcon-tv", > > + "allwinner,sun8i-a83t-tcon-tv"; > > + reg = <0x01c73000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; > > + clock-names = "ahb", "tcon-ch1"; > > + resets = <&ccu RST_BUS_TCON_TV0>; > > + reset-names = "lcd"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + tcon_tv0_in: port@0 { > > + reg = <0>; > > + }; > > + > > + tcon_tv0_out: port@1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > + > > + tcon_tv1: lcd-controller@1c74000 { > > + compatible = "allwinner,sun8i-r40-tcon-tv", > > + "allwinner,sun8i-a83t-tcon-tv"; > > + reg = <0x01c74000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; > > + clock-names = "ahb", "tcon-ch1"; > > + resets = <&ccu RST_BUS_TCON_TV1>; > > + reset-names = "lcd"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + tcon_tv1_in: port@0 { > > + reg = <0>; > > + }; > > + > > + tcon_tv1_out: port@1 { > > + reg = <1>; > > You are missing the remote-endpoints for all the TCON-TOP <-> TCON > connections. Also, on the driver side, there's no code to handle > dynamically mapping mixers to the TCONs that are being used. In the past we > had simple 1:1 mappings. This is no longer the case, and it needs to be > dealt with. How would TCON TOP driver know how to set muxes? There are no appropriate bingings for muxes, except for V4L2 subsystem, which doesn't really work here. Additionaly, how would HDMI know which TCON belongs to it to appropriately set possible_crtcs? Currently, my idea is that board DT creates wanted connections. Since there is only one valid connection for each mux, driver knows eactly what to write into mux register. HDMI driver can simply check which TCON connection is valid in HDMI input mux and select it in possible_crtcs. Please also note that mixer0 and mixer1 don't have same capabilities and you generally want mixer0 to be connected to main output. This is in contrast to DE1 SoCs, where both backends and both frontends have same capability. Best regards, Jernej > > ChenYu > > > + }; > > + }; > > + }; > > + > > > > gic: interrupt-controller@1c81000 { > > > > compatible = "arm,gic-400"; > > reg = <0x01c81000 0x1000>, > > > > @@ -461,6 +685,51 @@ > > > > #interrupt-cells = <3>; > > interrupts = > IRQ_TYPE_LEVEL_HIGH)>; > > > > }; > > > > + > > + hdmi: hdmi@1ee0000 { > > + compatible = "allwinner,sun8i-r40-dw-hdmi", > > + "allwinner,sun8i-a83t-dw-hdmi"; > > + reg = <0x01ee0000 0x10000>; > > + reg-io-width = <1>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_HDMI0>, <&ccu > > CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; > > + clock-names = "iahb", "isfr", "tmds"; > > + resets = <&ccu RST_BUS_HDMI1>; > > + reset-names = "ctrl"; > > + phys = <&hdmi_phy>; > > + phy-names = "hdmi-phy"; > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + hdmi_in: port@0 { > > + reg = <0>; > > + > > + hdmi_in_tcon_top: endpoint { > > + remote-endpoint = > > <&tcon_top_hdmi_out_hdmi>; + }; > > + }; > > + > > + hdmi_out: port@1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > + > > + hdmi_phy: hdmi-phy@1ef0000 { > > + compatible = "allwinner,sun8i-r40-hdmi-phy", > > + "allwinner,sun50i-a64-hdmi-phy"; > > + reg = <0x01ef0000 0x10000>; > > + clocks = <&ccu CLK_BUS_HDMI1>, <&ccu > > CLK_HDMI_SLOW>, + <&ccu 7>, <&ccu 16>; > > + clock-names = "bus", "mod", "pll-0", "pll-1"; > > + resets = <&ccu RST_BUS_HDMI0>; > > + reset-names = "phy"; > > + #phy-cells = <0>; > > + }; > > > > }; > > > > timer { > > > > -- > > 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jernej =?utf-8?B?xaBrcmFiZWM=?= Subject: Re: [PATCH v3 23/24] ARM: dts: sun8i: r40: Add HDMI pipeline Date: Thu, 28 Jun 2018 07:15:18 +0200 Message-ID: <21259128.K3MyN3b6Bq@jernej-laptop> References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-24-jernej.skrabec@siol.net> Reply-To: jernej.skrabec-gGgVlfcn5nU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Chen-Yu Tsai Cc: Maxime Ripard , Rob Herring , David Airlie , Gustavo Padovan , Maarten Lankhorst , Sean Paul , Mark Rutland , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk , linux-sunxi List-Id: devicetree@vger.kernel.org Dne =C4=8Detrtek, 28. junij 2018 ob 04:50:09 CEST je Chen-Yu Tsai napisal(a= ): > On Mon, Jun 25, 2018 at 8:03 PM, Jernej Skrabec = =20 wrote: > > Add all entries needed for HDMI to function properly. > >=20 > > Since R40 has highly configurable pipeline, both mixers and both TCON > > TVs are added. Board specific DT should then connect them together > > trough TCON TOP muxers to best fit the purpose of the board. > >=20 > > Signed-off-by: Jernej Skrabec > > --- > >=20 > > arch/arm/boot/dts/sun8i-r40.dtsi | 269 +++++++++++++++++++++++++++++++ > > 1 file changed, 269 insertions(+) > >=20 > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi > > b/arch/arm/boot/dts/sun8i-r40.dtsi index 173dcc1652d2..a2a75fb04caf > > 100644 > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi > > @@ -42,8 +42,11 @@ > >=20 > > */ > > =20 > > #include > >=20 > > +#include > >=20 > > #include > >=20 > > +#include Maxime, above line breaks compilation for build robot, sorry. > >=20 > > #include > >=20 > > +#include > >=20 > > / { > > =20 > > #address-cells =3D <1>; > >=20 > > @@ -99,12 +102,76 @@ > >=20 > > }; > > =20 > > }; > >=20 > > + de: display-engine { > > + compatible =3D "allwinner,sun8i-r40-display-engine", > > + "allwinner,sun8i-h3-display-engine"; >=20 > Given that the display pipeline looks different, they should not be > compatible. Ok. >=20 > > + allwinner,pipelines =3D <&mixer0>, <&mixer1>; > > + status =3D "disabled"; > > + }; > > + > >=20 > > soc { > > =20 > > compatible =3D "simple-bus"; > > #address-cells =3D <1>; > > #size-cells =3D <1>; > > ranges; > >=20 > > + display_clocks: clock@1000000 { > > + compatible =3D "allwinner,sun8i-r40-de2-clk", > > + "allwinner,sun8i-h3-de2-clk"; > > + reg =3D <0x01000000 0x100000>; > > + clocks =3D <&ccu CLK_DE>, > > + <&ccu CLK_BUS_DE>; > > + clock-names =3D "mod", > > + "bus"; > > + resets =3D <&ccu RST_BUS_DE>; > > + #clock-cells =3D <1>; > > + #reset-cells =3D <1>; > > + }; > > + > > + mixer0: mixer@1100000 { > > + compatible =3D "allwinner,sun8i-r40-de2-mixer-0= "; > > + reg =3D <0x01100000 0x100000>; > > + clocks =3D <&display_clocks CLK_BUS_MIXER0>, > > + <&display_clocks CLK_MIXER0>; > > + clock-names =3D "bus", > > + "mod"; > > + resets =3D <&display_clocks RST_MIXER0>; > > + > > + ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + mixer0_out: port@1 { > > + reg =3D <1>; > > + mixer0_out_tcon_top: endpoint { > > + remote-endpoint =3D > > <&tcon_top_mixer0_in_mixer0>; + }= ; > > + }; > > + }; > > + }; > > + > > + mixer1: mixer@1200000 { > > + compatible =3D "allwinner,sun8i-r40-de2-mixer-1= "; > > + reg =3D <0x01200000 0x100000>; > > + clocks =3D <&display_clocks CLK_BUS_MIXER1>, > > + <&display_clocks CLK_MIXER1>; > > + clock-names =3D "bus", > > + "mod"; > > + resets =3D <&display_clocks RST_WB>; > > + > > + ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + mixer1_out: port@1 { > > + reg =3D <1>; > > + mixer1_out_tcon_top: endpoint { > > + remote-endpoint =3D > > <&tcon_top_mixer1_in_mixer1>; + }= ; > > + }; > > + }; > > + }; > > + > >=20 > > nmi_intc: interrupt-controller@1c00030 { > > =20 > > compatible =3D "allwinner,sun7i-a20-sc-nmi"; > > interrupt-controller; > >=20 > > @@ -451,6 +518,163 @@ > >=20 > > #size-cells =3D <0>; > > =20 > > }; > >=20 > > + tcon_top: tcon-top@1c70000 { > > + compatible =3D "allwinner,sun8i-r40-tcon-top"; > > + reg =3D <0x01c70000 0x1000>; > > + clocks =3D <&ccu CLK_BUS_TCON_TOP>, > > + <&ccu CLK_TCON_TV0>, > > + <&ccu CLK_TVE0>, > > + <&ccu CLK_TCON_TV1>, > > + <&ccu CLK_TVE1>, > > + <&ccu CLK_DSI_DPHY>; > > + clock-names =3D "bus", > > + "tcon-tv0", > > + "tve0", > > + "tcon-tv1", > > + "tve1", > > + "dsi"; > > + clock-output-names =3D "tcon-top-tv0", > > + "tcon-top-tv1", > > + "tcon-top-dsi"; > > + resets =3D <&ccu RST_BUS_TCON_TOP>; > > + #clock-cells =3D <1>; > > + > > + ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + tcon_top_mixer0_in: port@0 { > > + reg =3D <0>; > > + > > + tcon_top_mixer0_in_mixer0: > > endpoint { + =20 > > remote-endpoint =3D <&mixer0_out_tcon_top>; + = =20 > > }; > > + }; > > + > > + tcon_top_mixer0_out: port@1 { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + reg =3D <1>; > > + > > + tcon_top_mixer0_out_tcon_lcd0: > > endpoint@0 { + reg =3D <0= >; > > + }; > > + > > + tcon_top_mixer0_out_tcon_lcd1: > > endpoint@1 { + reg =3D <1= >; > > + }; > > + > > + tcon_top_mixer0_out_tcon_tv0: > > endpoint@2 { + reg =3D <2= >; > > + }; > > + > > + tcon_top_mixer0_out_tcon_tv1: > > endpoint@3 { + reg =3D <3= >; > > + }; > > + }; > > + > > + tcon_top_mixer1_in: port@2 { > > + reg =3D <2>; > > + > > + tcon_top_mixer1_in_mixer1: > > endpoint { + =20 > > remote-endpoint =3D <&mixer1_out_tcon_top>; + = =20 > > }; > > + }; > > + > > + tcon_top_mixer1_out: port@3 { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + reg =3D <3>; > > + > > + tcon_top_mixer1_out_tcon_lcd0: > > endpoint@0 { + reg =3D <0= >; > > + }; > > + > > + tcon_top_mixer1_out_tcon_lcd1: > > endpoint@1 { + reg =3D <1= >; > > + }; > > + > > + tcon_top_mixer1_out_tcon_tv0: > > endpoint@2 { + reg =3D <2= >; > > + }; > > + > > + tcon_top_mixer1_out_tcon_tv1: > > endpoint@3 { + reg =3D <3= >; > > + }; > > + }; > > + > > + tcon_top_hdmi_in: port@4 { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + reg =3D <4>; > > + > > + tcon_top_hdmi_in_tcon_tv0: > > endpoint@0 { + reg =3D <0= >; > > + }; > > + > > + tcon_top_hdmi_in_tcon_tv1: > > endpoint@1 { + reg =3D <1= >; > > + }; > > + }; > > + > > + tcon_top_hdmi_out: port@5 { > > + reg =3D <5>; > > + > > + tcon_top_hdmi_out_hdmi: endpoin= t { > > + remote-endpoint =3D > > <&hdmi_in_tcon_top>; + }; > > + }; > > + }; > > + }; > > + > > + tcon_tv0: lcd-controller@1c73000 { > > + compatible =3D "allwinner,sun8i-r40-tcon-tv", > > + "allwinner,sun8i-a83t-tcon-tv"; > > + reg =3D <0x01c73000 0x1000>; > > + interrupts =3D = ; > > + clocks =3D <&ccu CLK_BUS_TCON_TV0>, <&tcon_top = 0>; > > + clock-names =3D "ahb", "tcon-ch1"; > > + resets =3D <&ccu RST_BUS_TCON_TV0>; > > + reset-names =3D "lcd"; > > + > > + ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + tcon_tv0_in: port@0 { > > + reg =3D <0>; > > + }; > > + > > + tcon_tv0_out: port@1 { > > + reg =3D <1>; > > + }; > > + }; > > + }; > > + > > + tcon_tv1: lcd-controller@1c74000 { > > + compatible =3D "allwinner,sun8i-r40-tcon-tv", > > + "allwinner,sun8i-a83t-tcon-tv"; > > + reg =3D <0x01c74000 0x1000>; > > + interrupts =3D = ; > > + clocks =3D <&ccu CLK_BUS_TCON_TV1>, <&tcon_top = 1>; > > + clock-names =3D "ahb", "tcon-ch1"; > > + resets =3D <&ccu RST_BUS_TCON_TV1>; > > + reset-names =3D "lcd"; > > + > > + ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + tcon_tv1_in: port@0 { > > + reg =3D <0>; > > + }; > > + > > + tcon_tv1_out: port@1 { > > + reg =3D <1>; >=20 > You are missing the remote-endpoints for all the TCON-TOP <-> TCON > connections. Also, on the driver side, there's no code to handle > dynamically mapping mixers to the TCONs that are being used. In the past = we > had simple 1:1 mappings. This is no longer the case, and it needs to be > dealt with. How would TCON TOP driver know how to set muxes? There are no appropriate= =20 bingings for muxes, except for V4L2 subsystem, which doesn't really work he= re. Additionaly, how would HDMI know which TCON belongs to it to appropriately = set=20 possible_crtcs? Currently, my idea is that board DT creates wanted connections. Since there= is=20 only one valid connection for each mux, driver knows eactly what to write i= nto=20 mux register. HDMI driver can simply check which TCON connection is valid i= n=20 HDMI input mux and select it in possible_crtcs. Please also note that mixer0 and mixer1 don't have same capabilities and yo= u=20 generally want mixer0 to be connected to main output. This is in contrast t= o=20 DE1 SoCs, where both backends and both frontends have same capability. Best regards, Jernej >=20 > ChenYu >=20 > > + }; > > + }; > > + }; > > + > >=20 > > gic: interrupt-controller@1c81000 { > > =20 > > compatible =3D "arm,gic-400"; > > reg =3D <0x01c81000 0x1000>, > >=20 > > @@ -461,6 +685,51 @@ > >=20 > > #interrupt-cells =3D <3>; > > interrupts =3D > IRQ_TYPE_LEVEL_HIGH)>; > > =20 > > }; > >=20 > > + > > + hdmi: hdmi@1ee0000 { > > + compatible =3D "allwinner,sun8i-r40-dw-hdmi", > > + "allwinner,sun8i-a83t-dw-hdmi"; > > + reg =3D <0x01ee0000 0x10000>; > > + reg-io-width =3D <1>; > > + interrupts =3D = ; > > + clocks =3D <&ccu CLK_BUS_HDMI0>, <&ccu > > CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; > > + clock-names =3D "iahb", "isfr", "tmds"; > > + resets =3D <&ccu RST_BUS_HDMI1>; > > + reset-names =3D "ctrl"; > > + phys =3D <&hdmi_phy>; > > + phy-names =3D "hdmi-phy"; > > + status =3D "disabled"; > > + > > + ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + hdmi_in: port@0 { > > + reg =3D <0>; > > + > > + hdmi_in_tcon_top: endpoint { > > + remote-endpoint =3D > > <&tcon_top_hdmi_out_hdmi>; + }; > > + }; > > + > > + hdmi_out: port@1 { > > + reg =3D <1>; > > + }; > > + }; > > + }; > > + > > + hdmi_phy: hdmi-phy@1ef0000 { > > + compatible =3D "allwinner,sun8i-r40-hdmi-phy", > > + "allwinner,sun50i-a64-hdmi-phy"; > > + reg =3D <0x01ef0000 0x10000>; > > + clocks =3D <&ccu CLK_BUS_HDMI1>, <&ccu > > CLK_HDMI_SLOW>, + <&ccu 7>, <&ccu 16>; > > + clock-names =3D "bus", "mod", "pll-0", "pll-1"; > > + resets =3D <&ccu RST_BUS_HDMI0>; > > + reset-names =3D "phy"; > > + #phy-cells =3D <0>; > > + }; > >=20 > > }; > > =20 > > timer { > >=20 > > -- > > 2.18.0 --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. From mboxrd@z Thu Jan 1 00:00:00 1970 From: jernej.skrabec@siol.net (Jernej =?utf-8?B?xaBrcmFiZWM=?=) Date: Thu, 28 Jun 2018 07:15:18 +0200 Subject: [PATCH v3 23/24] ARM: dts: sun8i: r40: Add HDMI pipeline In-Reply-To: References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-24-jernej.skrabec@siol.net> Message-ID: <21259128.K3MyN3b6Bq@jernej-laptop> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Dne ?etrtek, 28. junij 2018 ob 04:50:09 CEST je Chen-Yu Tsai napisal(a): > On Mon, Jun 25, 2018 at 8:03 PM, Jernej Skrabec wrote: > > Add all entries needed for HDMI to function properly. > > > > Since R40 has highly configurable pipeline, both mixers and both TCON > > TVs are added. Board specific DT should then connect them together > > trough TCON TOP muxers to best fit the purpose of the board. > > > > Signed-off-by: Jernej Skrabec > > --- > > > > arch/arm/boot/dts/sun8i-r40.dtsi | 269 +++++++++++++++++++++++++++++++ > > 1 file changed, 269 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi > > b/arch/arm/boot/dts/sun8i-r40.dtsi index 173dcc1652d2..a2a75fb04caf > > 100644 > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi > > @@ -42,8 +42,11 @@ > > > > */ > > > > #include > > > > +#include > > > > #include > > > > +#include Maxime, above line breaks compilation for build robot, sorry. > > > > #include > > > > +#include > > > > / { > > > > #address-cells = <1>; > > > > @@ -99,12 +102,76 @@ > > > > }; > > > > }; > > > > + de: display-engine { > > + compatible = "allwinner,sun8i-r40-display-engine", > > + "allwinner,sun8i-h3-display-engine"; > > Given that the display pipeline looks different, they should not be > compatible. Ok. > > > + allwinner,pipelines = <&mixer0>, <&mixer1>; > > + status = "disabled"; > > + }; > > + > > > > soc { > > > > compatible = "simple-bus"; > > #address-cells = <1>; > > #size-cells = <1>; > > ranges; > > > > + display_clocks: clock at 1000000 { > > + compatible = "allwinner,sun8i-r40-de2-clk", > > + "allwinner,sun8i-h3-de2-clk"; > > + reg = <0x01000000 0x100000>; > > + clocks = <&ccu CLK_DE>, > > + <&ccu CLK_BUS_DE>; > > + clock-names = "mod", > > + "bus"; > > + resets = <&ccu RST_BUS_DE>; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + }; > > + > > + mixer0: mixer at 1100000 { > > + compatible = "allwinner,sun8i-r40-de2-mixer-0"; > > + reg = <0x01100000 0x100000>; > > + clocks = <&display_clocks CLK_BUS_MIXER0>, > > + <&display_clocks CLK_MIXER0>; > > + clock-names = "bus", > > + "mod"; > > + resets = <&display_clocks RST_MIXER0>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mixer0_out: port at 1 { > > + reg = <1>; > > + mixer0_out_tcon_top: endpoint { > > + remote-endpoint = > > <&tcon_top_mixer0_in_mixer0>; + }; > > + }; > > + }; > > + }; > > + > > + mixer1: mixer at 1200000 { > > + compatible = "allwinner,sun8i-r40-de2-mixer-1"; > > + reg = <0x01200000 0x100000>; > > + clocks = <&display_clocks CLK_BUS_MIXER1>, > > + <&display_clocks CLK_MIXER1>; > > + clock-names = "bus", > > + "mod"; > > + resets = <&display_clocks RST_WB>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mixer1_out: port at 1 { > > + reg = <1>; > > + mixer1_out_tcon_top: endpoint { > > + remote-endpoint = > > <&tcon_top_mixer1_in_mixer1>; + }; > > + }; > > + }; > > + }; > > + > > > > nmi_intc: interrupt-controller at 1c00030 { > > > > compatible = "allwinner,sun7i-a20-sc-nmi"; > > interrupt-controller; > > > > @@ -451,6 +518,163 @@ > > > > #size-cells = <0>; > > > > }; > > > > + tcon_top: tcon-top at 1c70000 { > > + compatible = "allwinner,sun8i-r40-tcon-top"; > > + reg = <0x01c70000 0x1000>; > > + clocks = <&ccu CLK_BUS_TCON_TOP>, > > + <&ccu CLK_TCON_TV0>, > > + <&ccu CLK_TVE0>, > > + <&ccu CLK_TCON_TV1>, > > + <&ccu CLK_TVE1>, > > + <&ccu CLK_DSI_DPHY>; > > + clock-names = "bus", > > + "tcon-tv0", > > + "tve0", > > + "tcon-tv1", > > + "tve1", > > + "dsi"; > > + clock-output-names = "tcon-top-tv0", > > + "tcon-top-tv1", > > + "tcon-top-dsi"; > > + resets = <&ccu RST_BUS_TCON_TOP>; > > + #clock-cells = <1>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + tcon_top_mixer0_in: port at 0 { > > + reg = <0>; > > + > > + tcon_top_mixer0_in_mixer0: > > endpoint { + > > remote-endpoint = <&mixer0_out_tcon_top>; + > > }; > > + }; > > + > > + tcon_top_mixer0_out: port at 1 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <1>; > > + > > + tcon_top_mixer0_out_tcon_lcd0: > > endpoint at 0 { + reg = <0>; > > + }; > > + > > + tcon_top_mixer0_out_tcon_lcd1: > > endpoint at 1 { + reg = <1>; > > + }; > > + > > + tcon_top_mixer0_out_tcon_tv0: > > endpoint at 2 { + reg = <2>; > > + }; > > + > > + tcon_top_mixer0_out_tcon_tv1: > > endpoint at 3 { + reg = <3>; > > + }; > > + }; > > + > > + tcon_top_mixer1_in: port at 2 { > > + reg = <2>; > > + > > + tcon_top_mixer1_in_mixer1: > > endpoint { + > > remote-endpoint = <&mixer1_out_tcon_top>; + > > }; > > + }; > > + > > + tcon_top_mixer1_out: port at 3 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <3>; > > + > > + tcon_top_mixer1_out_tcon_lcd0: > > endpoint at 0 { + reg = <0>; > > + }; > > + > > + tcon_top_mixer1_out_tcon_lcd1: > > endpoint at 1 { + reg = <1>; > > + }; > > + > > + tcon_top_mixer1_out_tcon_tv0: > > endpoint at 2 { + reg = <2>; > > + }; > > + > > + tcon_top_mixer1_out_tcon_tv1: > > endpoint at 3 { + reg = <3>; > > + }; > > + }; > > + > > + tcon_top_hdmi_in: port at 4 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <4>; > > + > > + tcon_top_hdmi_in_tcon_tv0: > > endpoint at 0 { + reg = <0>; > > + }; > > + > > + tcon_top_hdmi_in_tcon_tv1: > > endpoint at 1 { + reg = <1>; > > + }; > > + }; > > + > > + tcon_top_hdmi_out: port at 5 { > > + reg = <5>; > > + > > + tcon_top_hdmi_out_hdmi: endpoint { > > + remote-endpoint = > > <&hdmi_in_tcon_top>; + }; > > + }; > > + }; > > + }; > > + > > + tcon_tv0: lcd-controller at 1c73000 { > > + compatible = "allwinner,sun8i-r40-tcon-tv", > > + "allwinner,sun8i-a83t-tcon-tv"; > > + reg = <0x01c73000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; > > + clock-names = "ahb", "tcon-ch1"; > > + resets = <&ccu RST_BUS_TCON_TV0>; > > + reset-names = "lcd"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + tcon_tv0_in: port at 0 { > > + reg = <0>; > > + }; > > + > > + tcon_tv0_out: port at 1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > + > > + tcon_tv1: lcd-controller at 1c74000 { > > + compatible = "allwinner,sun8i-r40-tcon-tv", > > + "allwinner,sun8i-a83t-tcon-tv"; > > + reg = <0x01c74000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; > > + clock-names = "ahb", "tcon-ch1"; > > + resets = <&ccu RST_BUS_TCON_TV1>; > > + reset-names = "lcd"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + tcon_tv1_in: port at 0 { > > + reg = <0>; > > + }; > > + > > + tcon_tv1_out: port at 1 { > > + reg = <1>; > > You are missing the remote-endpoints for all the TCON-TOP <-> TCON > connections. Also, on the driver side, there's no code to handle > dynamically mapping mixers to the TCONs that are being used. In the past we > had simple 1:1 mappings. This is no longer the case, and it needs to be > dealt with. How would TCON TOP driver know how to set muxes? There are no appropriate bingings for muxes, except for V4L2 subsystem, which doesn't really work here. Additionaly, how would HDMI know which TCON belongs to it to appropriately set possible_crtcs? Currently, my idea is that board DT creates wanted connections. Since there is only one valid connection for each mux, driver knows eactly what to write into mux register. HDMI driver can simply check which TCON connection is valid in HDMI input mux and select it in possible_crtcs. Please also note that mixer0 and mixer1 don't have same capabilities and you generally want mixer0 to be connected to main output. This is in contrast to DE1 SoCs, where both backends and both frontends have same capability. Best regards, Jernej > > ChenYu > > > + }; > > + }; > > + }; > > + > > > > gic: interrupt-controller at 1c81000 { > > > > compatible = "arm,gic-400"; > > reg = <0x01c81000 0x1000>, > > > > @@ -461,6 +685,51 @@ > > > > #interrupt-cells = <3>; > > interrupts = > IRQ_TYPE_LEVEL_HIGH)>; > > > > }; > > > > + > > + hdmi: hdmi at 1ee0000 { > > + compatible = "allwinner,sun8i-r40-dw-hdmi", > > + "allwinner,sun8i-a83t-dw-hdmi"; > > + reg = <0x01ee0000 0x10000>; > > + reg-io-width = <1>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_HDMI0>, <&ccu > > CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; > > + clock-names = "iahb", "isfr", "tmds"; > > + resets = <&ccu RST_BUS_HDMI1>; > > + reset-names = "ctrl"; > > + phys = <&hdmi_phy>; > > + phy-names = "hdmi-phy"; > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + hdmi_in: port at 0 { > > + reg = <0>; > > + > > + hdmi_in_tcon_top: endpoint { > > + remote-endpoint = > > <&tcon_top_hdmi_out_hdmi>; + }; > > + }; > > + > > + hdmi_out: port at 1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > + > > + hdmi_phy: hdmi-phy at 1ef0000 { > > + compatible = "allwinner,sun8i-r40-hdmi-phy", > > + "allwinner,sun50i-a64-hdmi-phy"; > > + reg = <0x01ef0000 0x10000>; > > + clocks = <&ccu CLK_BUS_HDMI1>, <&ccu > > CLK_HDMI_SLOW>, + <&ccu 7>, <&ccu 16>; > > + clock-names = "bus", "mod", "pll-0", "pll-1"; > > + resets = <&ccu RST_BUS_HDMI0>; > > + reset-names = "phy"; > > + #phy-cells = <0>; > > + }; > > > > }; > > > > timer { > > > > -- > > 2.18.0