[U-Boot-Users] [Fwd: Intel LXT971A PHY support]

[listmember at orkun.us <listmember@orkun.us>]

I did not get any comment for this. I was wondering the status of this patch.

Best regards,
Tolunay

---------------------------- Original Message ----------------------------
Hi,

I am in the process of creating a U-Boot port for Cogent CSB272 board
(PPC405)

Working from U-Boot 1.0.0 tarball sources, I got CSB272 running. I still
have some work done for it so I am not submitting CSB272 board support
yet. Maybe next week or so after I complete work on it and make sure Linux
boots OK.

Anyway, CSB272 board has Intel LXT971A PHY. I could not get this PHY
working initially. After investigation I have found:

1) LXT971A requires some recovery time (~300usec) before any register
access after reset. This is documented in the datasheet on page 70, table
40.

2) LXT971A requires some time after command is issued before polling
EMAC_STACR_OC is valid. I am not sure why this is needed but it is needed
for this particular PHY or otherwise it does not work. I have found this
to be minimum 32usec. I used 40usec for some safety margin.

Thus, to get it working I had to patch two shared files:

cpu/ppc4xx/miiphy.c
common/miiphyutil.c

The code added are conditional for each change and without those macro
definitions it compiles exactly as it is right now. The macros are as
follows (from my include/configs/csb272.h):

#define CONFIG_PHY_CMD_DELAY    40      /* PHY COMMAND delay            */
                                        /* 32usec min. for LXT971A      */
#define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */

Here is the patch (I can resend it as an attachment if format is broken)

--- u-boot-1.0.0/cpu/ppc4xx/miiphy.c	2003-09-02 18:08:13.000000000 -0500
+++ u-boot/cpu/ppc4xx/miiphy.c	2004-01-11 02:56:16.000000000 -0600 @@
-110,7 +110,9 @@ int miiphy_read (unsigned char addr, uns
 #if 0	/* test-only */
 	printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
 #endif
-
+#if defined(CONFIG_PHY_CMD_DELAY)
+	udelay(CONFIG_PHY_CMD_DELAY);	/* Intel LXT971A needs this */
+#endif
 	sta_reg = in32 (EMAC_STACR);
 	i = 0;
 	while ((sta_reg & EMAC_STACR_OC) == 0) {
@@ -166,6 +168,9 @@ int miiphy_write (unsigned char addr, un
 	memcpy (&sta_reg, &value, 2);	/* put in data */

 	out32 (EMAC_STACR, sta_reg);
+#if defined(CONFIG_PHY_CMD_DELAY)
+	udelay(CONFIG_PHY_CMD_DELAY);	/* Intel LXT971A needs this */
+#endif

 	/* wait for completion */
 	i = 0;
--- u-boot-1.0.0/common/miiphyutil.c	2003-10-08 17:33:00.000000000 -0500
+++ u-boot/common/miiphyutil.c	2004-01-11 22:42:42.249886108 -0600 @@
-103,6 +103,9 @@ int miiphy_reset (unsigned char addr)
 		return (-1);
 	}

+#if defined(CONFIG_PHY_RESET_DELAY)
+	udelay(CONFIG_PHY_RESET_DELAY);	/* Intel LXT971A needs this */
+#endif
 	/*
 	 * Poll the control register for the reset bit to go to 0 (it is *
auto-clearing).  This should happen within 0.5 seconds per the