From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF2F9C433E0 for ; Fri, 17 Jul 2020 05:28:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0222206BE for ; Fri, 17 Jul 2020 05:28:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="H3SECMdL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726104AbgGQF2r (ORCPT ); Fri, 17 Jul 2020 01:28:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725856AbgGQF2q (ORCPT ); Fri, 17 Jul 2020 01:28:46 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4ED9FC061755 for ; Thu, 16 Jul 2020 22:28:46 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id 17so15463515wmo.1 for ; Thu, 16 Jul 2020 22:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=3R841zjQJ873CPLugpq+yROuqcowWRWOM1I9YnQC0yw=; b=H3SECMdLBtoMFmBF8gwG7s68I1WI9g2z6KWf3uQwmopAlMDMBluxJ+IEfjBJ99v07N /dKcpfxRDsYE5eMibCoLsQ315MiIT3MdOv4AxOaq/CGFZsyxa1xVF18O/WlhtHY7j4gp rIcwEd9JNllTxFbyuIbucoyE0hI9NMONm+3mQbPi71qD4veRNfgQfrqn8EuFBlby/qll kRzmBoJRsV0VuonT4YsYyNc8x1zazXe+/fu9Sr0NryKm0Bgo/QJ+I/sJSpD8dTHzvesy XDUMDDtJoEsmjETrFP5jc3Fqyg3xnfOZDZc5D3aWo66R+BPcpISpS+Uv1tjuDxq38m5l okYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=3R841zjQJ873CPLugpq+yROuqcowWRWOM1I9YnQC0yw=; b=twM46ai86DtDP3UYkwgT5MSvw26K1lJwfY1/r6q1i0g8J7JosEmLD67yDNNI1IPNu+ fTLg+J1RMG4QIaPbn8Lfn8J96xTPaHvV4yYlaGLXTF5waMlh8Zx+lccmcHxPTM1SZjzd 6HBNd5Q8VXQqexmoMrEjbYlB5pjUlk/jShDWnYNLC502YMA5wv0/HbydhnNgapIrXWpe JH+Gf/FD0WsdBlHAy55Ik34C+ZmE7pzSRoF0NZ2v3oLxz/A9Mv2+x24G25lAyle+9TIK ZJFUcykY/vVeo3S4/GxqCwUi2MlJSKL85cIxMvro609ck73vmemNqYzZ2XD/eg3IGQp2 l/4g== X-Gm-Message-State: AOAM531muj5V5fjoGNr8XYYHdIdCGs5uglWoUysqR+kvIzs5APiLa+5E CPwUhEu8sARD08oPWoEW8NfZNw== X-Google-Smtp-Source: ABdhPJxvGoh8uftGdmqMg5u8XecWSwJcj4NaXq0/cWbuqhlLaZUM5md9QxgWeBOhWPoDygZC0p00kw== X-Received: by 2002:a1c:5453:: with SMTP id p19mr7244739wmi.41.1594963724692; Thu, 16 Jul 2020 22:28:44 -0700 (PDT) Received: from ?IPv6:2a01:e34:ed2f:f020:9880:a643:3e69:6393? ([2a01:e34:ed2f:f020:9880:a643:3e69:6393]) by smtp.googlemail.com with ESMTPSA id x1sm12158853wrp.10.2020.07.16.22.28.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Jul 2020 22:28:44 -0700 (PDT) Subject: Re: [PATCH v3 2/4] clocksource/drivers: Add CLINT timer driver To: Anup Patel Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Thomas Gleixner , Damien Le Moal , Atish Patra , Alistair Francis , linux-riscv , "linux-kernel@vger.kernel.org List" , devicetree@vger.kernel.org References: <20200715071506.10994-1-anup.patel@wdc.com> <20200715071506.10994-3-anup.patel@wdc.com> <9a36824c-ef23-de47-b52c-bf680067be6c@linaro.org> From: Daniel Lezcano Message-ID: <212eb026-e063-2b64-757b-9ca0e3f430bf@linaro.org> Date: Fri, 17 Jul 2020 07:28:43 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/07/2020 07:21, Anup Patel wrote: > On Fri, Jul 17, 2020 at 2:57 AM Daniel Lezcano > wrote: >> >> >> Hi Anup, >> >> >> On 15/07/2020 09:15, Anup Patel wrote: >>> The TIME CSR and SBI calls are not available in RISC-V M-mode so we >>> separate add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU >>> kernel). >> >> The description is confusing, please reword it and give a bit more >> information about the timer itself, especially, the IPI thing. > > Okay, will update. > >> >>> Signed-off-by: Anup Patel >>> --- >>> drivers/clocksource/Kconfig | 10 ++ >>> drivers/clocksource/Makefile | 1 + >>> drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++++++++++++++ >>> include/linux/cpuhotplug.h | 1 + >>> 4 files changed, 241 insertions(+) >>> create mode 100644 drivers/clocksource/timer-clint.c >>> >>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig >>> index 91418381fcd4..eabcf1cfb0c0 100644 >>> --- a/drivers/clocksource/Kconfig >>> +++ b/drivers/clocksource/Kconfig >>> @@ -658,6 +658,16 @@ config RISCV_TIMER >>> is accessed via both the SBI and the rdcycle instruction. This is >>> required for all RISC-V systems. >>> >>> +config CLINT_TIMER >>> + bool "Timer for the RISC-V platform" >>> + depends on GENERIC_SCHED_CLOCK && RISCV_M_MODE >>> + default y >>> + select TIMER_PROBE >>> + select TIMER_OF >>> + help >>> + This option enables the CLINT timer for RISC-V systems. The CLINT >>> + driver is usually used for NoMMU RISC-V systems. >> >> For the timer, we do silent option and let the platform config select >> it. Please refer to other timer option below as reference. > > Okay, I will use "default RISCV" instead of "default y" (just like other > timer Kconfig options). Preferably, select it from the platform's Kconfig. >> >>> config CSKY_MP_TIMER >>> bool "SMP Timer for the C-SKY platform" if COMPILE_TEST >>> depends on CSKY >>> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile >>> index bdda1a2e4097..18e700e703a0 100644 >>> --- a/drivers/clocksource/Makefile >>> +++ b/drivers/clocksource/Makefile >>> @@ -87,6 +87,7 @@ obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o >>> obj-$(CONFIG_X86_NUMACHIP) += numachip.o >>> obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o >>> obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o >>> +obj-$(CONFIG_CLINT_TIMER) += timer-clint.o >>> obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o >>> obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o >>> obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o >>> diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c >>> new file mode 100644 >>> index 000000000000..bfc38bb5a589 >>> --- /dev/null >>> +++ b/drivers/clocksource/timer-clint.c >>> @@ -0,0 +1,229 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +/* >>> + * Copyright (C) 2020 Western Digital Corporation or its affiliates. >>> + * >>> + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a >>> + * CLINT MMIO timer device. >>> + */ >>> + >>> +#define pr_fmt(fmt) "clint: " fmt >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#define CLINT_IPI_OFF 0 >>> +#define CLINT_TIMER_CMP_OFF 0x4000 >>> +#define CLINT_TIMER_VAL_OFF 0xbff8 >>> + >>> +/* CLINT manages IPI and Timer for RISC-V M-mode */ >>> +static u32 __iomem *clint_ipi_base; >>> +static u64 __iomem *clint_timer_cmp; >>> +static u64 __iomem *clint_timer_val; >>> +static unsigned long clint_timer_freq; >>> +static unsigned int clint_timer_irq; >>> + >>> +static void clint_send_ipi(const struct cpumask *target) >>> +{ >>> + unsigned int cpu; >>> + >>> + for_each_cpu(cpu, target) >>> + writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu)); >>> +} >>> + >>> +static void clint_clear_ipi(void) >>> +{ >>> + writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id())); >>> +} >>> + >>> +static struct riscv_ipi_ops clint_ipi_ops = { >>> + .ipi_inject = clint_send_ipi, >>> + .ipi_clear = clint_clear_ipi, >>> +}; >>> + >>> +#ifdef CONFIG_64BIT >>> +#define clint_get_cycles() readq_relaxed(clint_timer_val) >>> +#else >>> +#define clint_get_cycles() readl_relaxed(clint_timer_val) >>> +#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1) >>> +#endif >>> + >>> +#ifdef CONFIG_64BIT >>> +static u64 clint_get_cycles64(void) >>> +{ >>> + return clint_get_cycles(); >>> +} >>> +#else /* CONFIG_64BIT */ >>> +static u64 clint_get_cycles64(void) >>> +{ >>> + u32 hi, lo; >>> + >>> + do { >>> + hi = clint_get_cycles_hi(); >>> + lo = clint_get_cycles(); >>> + } while (hi != clint_get_cycles_hi()); >>> + >>> + return ((u64)hi << 32) | lo; >>> +} >>> +#endif /* CONFIG_64BIT */ >>> +static int clint_clock_next_event(unsigned long delta, >>> + struct clock_event_device *ce) >>> +{ >>> + void __iomem *r = clint_timer_cmp + >>> + cpuid_to_hartid_map(smp_processor_id()); >>> + >>> + csr_set(CSR_IE, IE_TIE); >>> + writeq_relaxed(clint_get_cycles64() + delta, r); >>> + return 0; >>> +} >>> + >>> +static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = { >>> + .name = "clint_clockevent", >>> + .features = CLOCK_EVT_FEAT_ONESHOT, >>> + .rating = 100, >>> + .set_next_event = clint_clock_next_event, >>> +}; >>> + >>> +static u64 clint_rdtime(struct clocksource *cs) >>> +{ >>> + return readq_relaxed(clint_timer_val); >>> +} >>> + >>> +static u64 notrace clint_sched_clock(void) >>> +{ >>> + return readq_relaxed(clint_timer_val); >>> +} >>> + >>> +static struct clocksource clint_clocksource = { >>> + .name = "clint_clocksource", >>> + .rating = 300, >>> + .mask = CLOCKSOURCE_MASK(64), >>> + .flags = CLOCK_SOURCE_IS_CONTINUOUS, >>> + .read = clint_rdtime, >> >> What if !CONFIG_64BIT > > The CLINT counter is 64bit for both 32bit and 64bit systems > but I should have used clint_get_cycles64() in clint_rdtime(). > I will update it. > >> >>> +}; >>> + >>> +static int clint_timer_starting_cpu(unsigned int cpu) >>> +{ >>> + struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu); >>> + >>> + ce->cpumask = cpumask_of(cpu); >>> + clockevents_config_and_register(ce, clint_timer_freq, 200, ULONG_MAX); >> >> The function is not immune against registering the same clockevents. If >> the CPU is hotplugged several times, this function will be called again >> and again. Why not rely on a for_each_possible_cpu loop in the init >> function ? >> >>> + enable_percpu_irq(clint_timer_irq, >>> + irq_get_trigger_type(clint_timer_irq)); >> >> Why do you want to enable / disable the interrrupts ? The should be >> already handle by the hotplug framework no ? > > The perCPU interrupts are not enabled by default. We have to > explicitly enable/disable perCPU interrupts in CPU hotplug callbacks. > Isn't is possible to do that in the probe/init function ? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7036DC433E2 for ; Fri, 17 Jul 2020 05:28:56 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 28331206BE for ; Fri, 17 Jul 2020 05:28:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="LsI3cvXY"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="H3SECMdL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 28331206BE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=n7x1hQyUlO03qOlBKcE2mPCcIw056O/gGcNjqz/uSAI=; b=LsI3cvXYtUGZvCd0c/JVPhsOM jXYIwhD5RbTejFRWf8UqBg/vPoBahK4PbUbpG3PX7HLO+SFdPKZDnohd0wJW1uFTKAVz8B8v0nxy+ yWWXMUNWqs2B5o/n2uev0nUs1WWPFervvVtO4sssNtqMlEV0BlfHgluSsi8OsZl8Vzy0VV1/++2qa X6kO6TUqmakMnIL8QD12EfTVCtZvnC/m2DG9CM15ftArO2AtyumK5czL3oYwynP93Easd3rPJinu0 NEX0inlqyQLbGXUN9xPDI3bVgywW+h9+9NzW3+axXe9Wx9p6HhMYqIOrvaRBouGvijCgrNytz3wl1 v70rUwvJA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwIvR-0005c5-I7; Fri, 17 Jul 2020 05:28:49 +0000 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwIvP-0005bP-3c for linux-riscv@lists.infradead.org; Fri, 17 Jul 2020 05:28:48 +0000 Received: by mail-wm1-x343.google.com with SMTP id w3so15438835wmi.4 for ; Thu, 16 Jul 2020 22:28:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=3R841zjQJ873CPLugpq+yROuqcowWRWOM1I9YnQC0yw=; b=H3SECMdLBtoMFmBF8gwG7s68I1WI9g2z6KWf3uQwmopAlMDMBluxJ+IEfjBJ99v07N /dKcpfxRDsYE5eMibCoLsQ315MiIT3MdOv4AxOaq/CGFZsyxa1xVF18O/WlhtHY7j4gp rIcwEd9JNllTxFbyuIbucoyE0hI9NMONm+3mQbPi71qD4veRNfgQfrqn8EuFBlby/qll kRzmBoJRsV0VuonT4YsYyNc8x1zazXe+/fu9Sr0NryKm0Bgo/QJ+I/sJSpD8dTHzvesy XDUMDDtJoEsmjETrFP5jc3Fqyg3xnfOZDZc5D3aWo66R+BPcpISpS+Uv1tjuDxq38m5l okYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=3R841zjQJ873CPLugpq+yROuqcowWRWOM1I9YnQC0yw=; b=auBrXs6gU/UdHpYNTAR6+ZSmoDSVtZOuNf9rbLocDG4QaNnYZWfAyegsDgEEMqzgXq MuYUu5YUIjHwjIvT6ZBW7Q+sG7ulQOkcGNdm9XSpZzWb1hoJOgg3I7DNRyioqXOxhd9i o2P261OOwRRyVKI5sDl9XaJ3Tc8X8VAgO8+ocpu0DaSbFtq/bCE2GtkgX8qeo4lzjqNK y+K6D8gph/Pu9t95mtNNN6AFYIVZj6NwvFH/iPMsO1QvtcqvsB7JPU0BKnhwIIZp7gMN T329cXyMiaHEU3G61cotBFyKJVPdjcFKI7IYZYob3ueoxWCvi5/Om0zco1Av9a3pGFW/ gUNw== X-Gm-Message-State: AOAM532vXf6FVghwhtlgq3eEbs/xzAJMKCqQ3DY/FijssRps2o6fUHpL Nc7yAGh60adWi8s48Ne6yVYsLfISN7o= X-Google-Smtp-Source: ABdhPJxvGoh8uftGdmqMg5u8XecWSwJcj4NaXq0/cWbuqhlLaZUM5md9QxgWeBOhWPoDygZC0p00kw== X-Received: by 2002:a1c:5453:: with SMTP id p19mr7244739wmi.41.1594963724692; Thu, 16 Jul 2020 22:28:44 -0700 (PDT) Received: from ?IPv6:2a01:e34:ed2f:f020:9880:a643:3e69:6393? ([2a01:e34:ed2f:f020:9880:a643:3e69:6393]) by smtp.googlemail.com with ESMTPSA id x1sm12158853wrp.10.2020.07.16.22.28.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Jul 2020 22:28:44 -0700 (PDT) Subject: Re: [PATCH v3 2/4] clocksource/drivers: Add CLINT timer driver To: Anup Patel References: <20200715071506.10994-1-anup.patel@wdc.com> <20200715071506.10994-3-anup.patel@wdc.com> <9a36824c-ef23-de47-b52c-bf680067be6c@linaro.org> From: Daniel Lezcano Message-ID: <212eb026-e063-2b64-757b-9ca0e3f430bf@linaro.org> Date: Fri, 17 Jul 2020 07:28:43 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_012847_178525_88ACEF57 X-CRM114-Status: GOOD ( 28.90 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Damien Le Moal , Albert Ou , Anup Patel , "linux-kernel@vger.kernel.org List" , Atish Patra , Rob Herring , Palmer Dabbelt , Paul Walmsley , Alistair Francis , Thomas Gleixner , linux-riscv Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gMTcvMDcvMjAyMCAwNzoyMSwgQW51cCBQYXRlbCB3cm90ZToKPiBPbiBGcmksIEp1bCAxNywg MjAyMCBhdCAyOjU3IEFNIERhbmllbCBMZXpjYW5vCj4gPGRhbmllbC5sZXpjYW5vQGxpbmFyby5v cmc+IHdyb3RlOgo+Pgo+Pgo+PiBIaSBBbnVwLAo+Pgo+Pgo+PiBPbiAxNS8wNy8yMDIwIDA5OjE1 LCBBbnVwIFBhdGVsIHdyb3RlOgo+Pj4gVGhlIFRJTUUgQ1NSIGFuZCBTQkkgY2FsbHMgYXJlIG5v dCBhdmFpbGFibGUgaW4gUklTQy1WIE0tbW9kZSBzbyB3ZQo+Pj4gc2VwYXJhdGUgYWRkIENMSU5U IGRyaXZlciBmb3IgTGludXggUklTQy1WIE0tbW9kZSAoaS5lLiBSSVNDLVYgTm9NTVUKPj4+IGtl cm5lbCkuCj4+Cj4+IFRoZSBkZXNjcmlwdGlvbiBpcyBjb25mdXNpbmcsIHBsZWFzZSByZXdvcmQg aXQgYW5kIGdpdmUgYSBiaXQgbW9yZQo+PiBpbmZvcm1hdGlvbiBhYm91dCB0aGUgdGltZXIgaXRz ZWxmLCBlc3BlY2lhbGx5LCB0aGUgSVBJIHRoaW5nLgo+IAo+IE9rYXksIHdpbGwgdXBkYXRlLgo+ IAo+Pgo+Pj4gU2lnbmVkLW9mZi1ieTogQW51cCBQYXRlbCA8YW51cC5wYXRlbEB3ZGMuY29tPgo+ Pj4gLS0tCj4+PiAgZHJpdmVycy9jbG9ja3NvdXJjZS9LY29uZmlnICAgICAgIHwgIDEwICsrCj4+ PiAgZHJpdmVycy9jbG9ja3NvdXJjZS9NYWtlZmlsZSAgICAgIHwgICAxICsKPj4+ICBkcml2ZXJz L2Nsb2Nrc291cmNlL3RpbWVyLWNsaW50LmMgfCAyMjkgKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrCj4+PiAgaW5jbHVkZS9saW51eC9jcHVob3RwbHVnLmggICAgICAgIHwgICAxICsKPj4+ ICA0IGZpbGVzIGNoYW5nZWQsIDI0MSBpbnNlcnRpb25zKCspCj4+PiAgY3JlYXRlIG1vZGUgMTAw NjQ0IGRyaXZlcnMvY2xvY2tzb3VyY2UvdGltZXItY2xpbnQuYwo+Pj4KPj4+IGRpZmYgLS1naXQg YS9kcml2ZXJzL2Nsb2Nrc291cmNlL0tjb25maWcgYi9kcml2ZXJzL2Nsb2Nrc291cmNlL0tjb25m aWcKPj4+IGluZGV4IDkxNDE4MzgxZmNkNC4uZWFiY2YxY2ZiMGMwIDEwMDY0NAo+Pj4gLS0tIGEv ZHJpdmVycy9jbG9ja3NvdXJjZS9LY29uZmlnCj4+PiArKysgYi9kcml2ZXJzL2Nsb2Nrc291cmNl L0tjb25maWcKPj4+IEBAIC02NTgsNiArNjU4LDE2IEBAIGNvbmZpZyBSSVNDVl9USU1FUgo+Pj4g ICAgICAgICBpcyBhY2Nlc3NlZCB2aWEgYm90aCB0aGUgU0JJIGFuZCB0aGUgcmRjeWNsZSBpbnN0 cnVjdGlvbi4gIFRoaXMgaXMKPj4+ICAgICAgICAgcmVxdWlyZWQgZm9yIGFsbCBSSVNDLVYgc3lz dGVtcy4KPj4+Cj4+PiArY29uZmlnIENMSU5UX1RJTUVSCj4+PiArICAgICBib29sICJUaW1lciBm b3IgdGhlIFJJU0MtViBwbGF0Zm9ybSIKPj4+ICsgICAgIGRlcGVuZHMgb24gR0VORVJJQ19TQ0hF RF9DTE9DSyAmJiBSSVNDVl9NX01PREUKPj4+ICsgICAgIGRlZmF1bHQgeQo+Pj4gKyAgICAgc2Vs ZWN0IFRJTUVSX1BST0JFCj4+PiArICAgICBzZWxlY3QgVElNRVJfT0YKPj4+ICsgICAgIGhlbHAK Pj4+ICsgICAgICAgVGhpcyBvcHRpb24gZW5hYmxlcyB0aGUgQ0xJTlQgdGltZXIgZm9yIFJJU0Mt ViBzeXN0ZW1zLiBUaGUgQ0xJTlQKPj4+ICsgICAgICAgZHJpdmVyIGlzIHVzdWFsbHkgdXNlZCBm b3IgTm9NTVUgUklTQy1WIHN5c3RlbXMuCj4+Cj4+IEZvciB0aGUgdGltZXIsIHdlIGRvIHNpbGVu dCBvcHRpb24gYW5kIGxldCB0aGUgcGxhdGZvcm0gY29uZmlnIHNlbGVjdAo+PiBpdC4gUGxlYXNl IHJlZmVyIHRvIG90aGVyIHRpbWVyIG9wdGlvbiBiZWxvdyBhcyByZWZlcmVuY2UuCj4gCj4gT2th eSwgSSB3aWxsIHVzZSAiZGVmYXVsdCBSSVNDViIgaW5zdGVhZCBvZiAiZGVmYXVsdCB5IiAoanVz dCBsaWtlIG90aGVyCj4gdGltZXIgS2NvbmZpZyBvcHRpb25zKS4KClByZWZlcmFibHksIHNlbGVj dCBpdCBmcm9tIHRoZSBwbGF0Zm9ybSdzIEtjb25maWcuCgo+Pgo+Pj4gIGNvbmZpZyBDU0tZX01Q X1RJTUVSCj4+PiAgICAgICBib29sICJTTVAgVGltZXIgZm9yIHRoZSBDLVNLWSBwbGF0Zm9ybSIg aWYgQ09NUElMRV9URVNUCj4+PiAgICAgICBkZXBlbmRzIG9uIENTS1kKPj4+IGRpZmYgLS1naXQg YS9kcml2ZXJzL2Nsb2Nrc291cmNlL01ha2VmaWxlIGIvZHJpdmVycy9jbG9ja3NvdXJjZS9NYWtl ZmlsZQo+Pj4gaW5kZXggYmRkYTFhMmU0MDk3Li4xOGU3MDBlNzAzYTAgMTAwNjQ0Cj4+PiAtLS0g YS9kcml2ZXJzL2Nsb2Nrc291cmNlL01ha2VmaWxlCj4+PiArKysgYi9kcml2ZXJzL2Nsb2Nrc291 cmNlL01ha2VmaWxlCj4+PiBAQCAtODcsNiArODcsNyBAQCBvYmotJChDT05GSUdfQ0xLU1JDX1NU X0xQQykgICAgICAgICArPSBjbGtzcmNfc3RfbHBjLm8KPj4+ICBvYmotJChDT05GSUdfWDg2X05V TUFDSElQKSAgICAgICAgICAgKz0gbnVtYWNoaXAubwo+Pj4gIG9iai0kKENPTkZJR19BVENQSVQx MDBfVElNRVIpICAgICAgICAgICAgICAgICs9IHRpbWVyLWF0Y3BpdDEwMC5vCj4+PiAgb2JqLSQo Q09ORklHX1JJU0NWX1RJTUVSKSAgICAgICAgICAgICs9IHRpbWVyLXJpc2N2Lm8KPj4+ICtvYmot JChDT05GSUdfQ0xJTlRfVElNRVIpICAgICAgICAgICAgKz0gdGltZXItY2xpbnQubwo+Pj4gIG9i ai0kKENPTkZJR19DU0tZX01QX1RJTUVSKSAgICAgICAgICArPSB0aW1lci1tcC1jc2t5Lm8KPj4+ ICBvYmotJChDT05GSUdfR1g2NjA1U19USU1FUikgICAgICAgICAgKz0gdGltZXItZ3g2NjA1cy5v Cj4+PiAgb2JqLSQoQ09ORklHX0hZUEVSVl9USU1FUikgICAgICAgICAgICs9IGh5cGVydl90aW1l ci5vCj4+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9jbG9ja3NvdXJjZS90aW1lci1jbGludC5jIGIv ZHJpdmVycy9jbG9ja3NvdXJjZS90aW1lci1jbGludC5jCj4+PiBuZXcgZmlsZSBtb2RlIDEwMDY0 NAo+Pj4gaW5kZXggMDAwMDAwMDAwMDAwLi5iZmMzOGJiNWE1ODkKPj4+IC0tLSAvZGV2L251bGwK Pj4+ICsrKyBiL2RyaXZlcnMvY2xvY2tzb3VyY2UvdGltZXItY2xpbnQuYwo+Pj4gQEAgLTAsMCAr MSwyMjkgQEAKPj4+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMAo+Pj4gKy8q Cj4+PiArICogQ29weXJpZ2h0IChDKSAyMDIwIFdlc3Rlcm4gRGlnaXRhbCBDb3Jwb3JhdGlvbiBv ciBpdHMgYWZmaWxpYXRlcy4KPj4+ICsgKgo+Pj4gKyAqIE1vc3Qgb2YgdGhlIE0tbW9kZSAoaS5l LiBOb01NVSkgUklTQy1WIHN5c3RlbXMgdXN1YWxseSBoYXZlIGEKPj4+ICsgKiBDTElOVCBNTUlP IHRpbWVyIGRldmljZS4KPj4+ICsgKi8KPj4+ICsKPj4+ICsjZGVmaW5lIHByX2ZtdChmbXQpICJj bGludDogIiBmbXQKPj4+ICsjaW5jbHVkZSA8bGludXgvYml0b3BzLmg+Cj4+PiArI2luY2x1ZGUg PGxpbnV4L2Nsb2Nrc291cmNlLmg+Cj4+PiArI2luY2x1ZGUgPGxpbnV4L2Nsb2NrY2hpcHMuaD4K Pj4+ICsjaW5jbHVkZSA8bGludXgvY3B1Lmg+Cj4+PiArI2luY2x1ZGUgPGxpbnV4L2RlbGF5Lmg+ Cj4+PiArI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5oPgo+Pj4gKyNpbmNsdWRlIDxsaW51eC9vZl9h ZGRyZXNzLmg+Cj4+PiArI2luY2x1ZGUgPGxpbnV4L3NjaGVkX2Nsb2NrLmg+Cj4+PiArI2luY2x1 ZGUgPGxpbnV4L2lvLTY0LW5vbmF0b21pYy1sby1oaS5oPgo+Pj4gKyNpbmNsdWRlIDxsaW51eC9p bnRlcnJ1cHQuaD4KPj4+ICsjaW5jbHVkZSA8bGludXgvb2ZfaXJxLmg+Cj4+PiArI2luY2x1ZGUg PGxpbnV4L3NtcC5oPgo+Pj4gKwo+Pj4gKyNkZWZpbmUgQ0xJTlRfSVBJX09GRiAgICAgICAgICAg ICAgICAwCj4+PiArI2RlZmluZSBDTElOVF9USU1FUl9DTVBfT0ZGICAweDQwMDAKPj4+ICsjZGVm aW5lIENMSU5UX1RJTUVSX1ZBTF9PRkYgIDB4YmZmOAo+Pj4gKwo+Pj4gKy8qIENMSU5UIG1hbmFn ZXMgSVBJIGFuZCBUaW1lciBmb3IgUklTQy1WIE0tbW9kZSAgKi8KPj4+ICtzdGF0aWMgdTMyIF9f aW9tZW0gKmNsaW50X2lwaV9iYXNlOwo+Pj4gK3N0YXRpYyB1NjQgX19pb21lbSAqY2xpbnRfdGlt ZXJfY21wOwo+Pj4gK3N0YXRpYyB1NjQgX19pb21lbSAqY2xpbnRfdGltZXJfdmFsOwo+Pj4gK3N0 YXRpYyB1bnNpZ25lZCBsb25nIGNsaW50X3RpbWVyX2ZyZXE7Cj4+PiArc3RhdGljIHVuc2lnbmVk IGludCBjbGludF90aW1lcl9pcnE7Cj4+PiArCj4+PiArc3RhdGljIHZvaWQgY2xpbnRfc2VuZF9p cGkoY29uc3Qgc3RydWN0IGNwdW1hc2sgKnRhcmdldCkKPj4+ICt7Cj4+PiArICAgICB1bnNpZ25l ZCBpbnQgY3B1Owo+Pj4gKwo+Pj4gKyAgICAgZm9yX2VhY2hfY3B1KGNwdSwgdGFyZ2V0KQo+Pj4g KyAgICAgICAgICAgICB3cml0ZWwoMSwgY2xpbnRfaXBpX2Jhc2UgKyBjcHVpZF90b19oYXJ0aWRf bWFwKGNwdSkpOwo+Pj4gK30KPj4+ICsKPj4+ICtzdGF0aWMgdm9pZCBjbGludF9jbGVhcl9pcGko dm9pZCkKPj4+ICt7Cj4+PiArICAgICB3cml0ZWwoMCwgY2xpbnRfaXBpX2Jhc2UgKyBjcHVpZF90 b19oYXJ0aWRfbWFwKHNtcF9wcm9jZXNzb3JfaWQoKSkpOwo+Pj4gK30KPj4+ICsKPj4+ICtzdGF0 aWMgc3RydWN0IHJpc2N2X2lwaV9vcHMgY2xpbnRfaXBpX29wcyA9IHsKPj4+ICsgICAgIC5pcGlf aW5qZWN0ID0gY2xpbnRfc2VuZF9pcGksCj4+PiArICAgICAuaXBpX2NsZWFyID0gY2xpbnRfY2xl YXJfaXBpLAo+Pj4gK307Cj4+PiArCj4+PiArI2lmZGVmIENPTkZJR182NEJJVAo+Pj4gKyNkZWZp bmUgY2xpbnRfZ2V0X2N5Y2xlcygpICAgcmVhZHFfcmVsYXhlZChjbGludF90aW1lcl92YWwpCj4+ PiArI2Vsc2UKPj4+ICsjZGVmaW5lIGNsaW50X2dldF9jeWNsZXMoKSAgIHJlYWRsX3JlbGF4ZWQo Y2xpbnRfdGltZXJfdmFsKQo+Pj4gKyNkZWZpbmUgY2xpbnRfZ2V0X2N5Y2xlc19oaSgpICAgICAg ICByZWFkbF9yZWxheGVkKCgodTMyICopY2xpbnRfdGltZXJfdmFsKSArIDEpCj4+PiArI2VuZGlm Cj4+PiArCj4+PiArI2lmZGVmIENPTkZJR182NEJJVAo+Pj4gK3N0YXRpYyB1NjQgY2xpbnRfZ2V0 X2N5Y2xlczY0KHZvaWQpCj4+PiArewo+Pj4gKyAgICAgcmV0dXJuIGNsaW50X2dldF9jeWNsZXMo KTsKPj4+ICt9Cj4+PiArI2Vsc2UgLyogQ09ORklHXzY0QklUICovCj4+PiArc3RhdGljIHU2NCBj bGludF9nZXRfY3ljbGVzNjQodm9pZCkKPj4+ICt7Cj4+PiArICAgICB1MzIgaGksIGxvOwo+Pj4g Kwo+Pj4gKyAgICAgZG8gewo+Pj4gKyAgICAgICAgICAgICBoaSA9IGNsaW50X2dldF9jeWNsZXNf aGkoKTsKPj4+ICsgICAgICAgICAgICAgbG8gPSBjbGludF9nZXRfY3ljbGVzKCk7Cj4+PiArICAg ICB9IHdoaWxlIChoaSAhPSBjbGludF9nZXRfY3ljbGVzX2hpKCkpOwo+Pj4gKwo+Pj4gKyAgICAg cmV0dXJuICgodTY0KWhpIDw8IDMyKSB8IGxvOwo+Pj4gK30KPj4+ICsjZW5kaWYgLyogQ09ORklH XzY0QklUICovCj4+PiArc3RhdGljIGludCBjbGludF9jbG9ja19uZXh0X2V2ZW50KHVuc2lnbmVk IGxvbmcgZGVsdGEsCj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBzdHJ1Y3Qg Y2xvY2tfZXZlbnRfZGV2aWNlICpjZSkKPj4+ICt7Cj4+PiArICAgICB2b2lkIF9faW9tZW0gKnIg PSBjbGludF90aW1lcl9jbXAgKwo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgY3B1aWRfdG9f aGFydGlkX21hcChzbXBfcHJvY2Vzc29yX2lkKCkpOwo+Pj4gKwo+Pj4gKyAgICAgY3NyX3NldChD U1JfSUUsIElFX1RJRSk7Cj4+PiArICAgICB3cml0ZXFfcmVsYXhlZChjbGludF9nZXRfY3ljbGVz NjQoKSArIGRlbHRhLCByKTsKPj4+ICsgICAgIHJldHVybiAwOwo+Pj4gK30KPj4+ICsKPj4+ICtz dGF0aWMgREVGSU5FX1BFUl9DUFUoc3RydWN0IGNsb2NrX2V2ZW50X2RldmljZSwgY2xpbnRfY2xv Y2tfZXZlbnQpID0gewo+Pj4gKyAgICAgLm5hbWUgICAgICAgICAgICAgICAgICAgPSAiY2xpbnRf Y2xvY2tldmVudCIsCj4+PiArICAgICAuZmVhdHVyZXMgICAgICAgICAgICAgICA9IENMT0NLX0VW VF9GRUFUX09ORVNIT1QsCj4+PiArICAgICAucmF0aW5nICAgICAgICAgPSAxMDAsCj4+PiArICAg ICAuc2V0X25leHRfZXZlbnQgPSBjbGludF9jbG9ja19uZXh0X2V2ZW50LAo+Pj4gK307Cj4+PiAr Cj4+PiArc3RhdGljIHU2NCBjbGludF9yZHRpbWUoc3RydWN0IGNsb2Nrc291cmNlICpjcykKPj4+ ICt7Cj4+PiArICAgICByZXR1cm4gcmVhZHFfcmVsYXhlZChjbGludF90aW1lcl92YWwpOwo+Pj4g K30KPj4+ICsKPj4+ICtzdGF0aWMgdTY0IG5vdHJhY2UgY2xpbnRfc2NoZWRfY2xvY2sodm9pZCkK Pj4+ICt7Cj4+PiArICAgICByZXR1cm4gcmVhZHFfcmVsYXhlZChjbGludF90aW1lcl92YWwpOwo+ Pj4gK30KPj4+ICsKPj4+ICtzdGF0aWMgc3RydWN0IGNsb2Nrc291cmNlIGNsaW50X2Nsb2Nrc291 cmNlID0gewo+Pj4gKyAgICAgLm5hbWUgICAgICAgICAgID0gImNsaW50X2Nsb2Nrc291cmNlIiwK Pj4+ICsgICAgIC5yYXRpbmcgPSAzMDAsCj4+PiArICAgICAubWFzayAgICAgICAgICAgPSBDTE9D S1NPVVJDRV9NQVNLKDY0KSwKPj4+ICsgICAgIC5mbGFncyAgICAgICAgICA9IENMT0NLX1NPVVJD RV9JU19DT05USU5VT1VTLAo+Pj4gKyAgICAgLnJlYWQgICAgICAgICAgID0gY2xpbnRfcmR0aW1l LAo+Pgo+PiBXaGF0IGlmICFDT05GSUdfNjRCSVQKPiAKPiBUaGUgQ0xJTlQgY291bnRlciBpcyA2 NGJpdCBmb3IgYm90aCAzMmJpdCBhbmQgNjRiaXQgc3lzdGVtcwo+IGJ1dCBJIHNob3VsZCBoYXZl IHVzZWQgY2xpbnRfZ2V0X2N5Y2xlczY0KCkgaW4gY2xpbnRfcmR0aW1lKCkuCj4gSSB3aWxsIHVw ZGF0ZSBpdC4KPiAKPj4KPj4+ICt9Owo+Pj4gKwo+Pj4gK3N0YXRpYyBpbnQgY2xpbnRfdGltZXJf c3RhcnRpbmdfY3B1KHVuc2lnbmVkIGludCBjcHUpCj4+PiArewo+Pj4gKyAgICAgc3RydWN0IGNs b2NrX2V2ZW50X2RldmljZSAqY2UgPSBwZXJfY3B1X3B0cigmY2xpbnRfY2xvY2tfZXZlbnQsIGNw dSk7Cj4+PiArCj4+PiArICAgICBjZS0+Y3B1bWFzayA9IGNwdW1hc2tfb2YoY3B1KTsKPj4+ICsg ICAgIGNsb2NrZXZlbnRzX2NvbmZpZ19hbmRfcmVnaXN0ZXIoY2UsIGNsaW50X3RpbWVyX2ZyZXEs IDIwMCwgVUxPTkdfTUFYKTsKPj4KPj4gVGhlIGZ1bmN0aW9uIGlzIG5vdCBpbW11bmUgYWdhaW5z dCByZWdpc3RlcmluZyB0aGUgc2FtZSBjbG9ja2V2ZW50cy4gSWYKPj4gdGhlIENQVSBpcyBob3Rw bHVnZ2VkIHNldmVyYWwgdGltZXMsIHRoaXMgZnVuY3Rpb24gd2lsbCBiZSBjYWxsZWQgYWdhaW4K Pj4gYW5kIGFnYWluLiBXaHkgbm90IHJlbHkgb24gYSBmb3JfZWFjaF9wb3NzaWJsZV9jcHUgbG9v cCBpbiB0aGUgaW5pdAo+PiBmdW5jdGlvbiA/Cj4+Cj4+PiArICAgICBlbmFibGVfcGVyY3B1X2ly cShjbGludF90aW1lcl9pcnEsCj4+PiArICAgICAgICAgICAgICAgICAgICAgICBpcnFfZ2V0X3Ry aWdnZXJfdHlwZShjbGludF90aW1lcl9pcnEpKTsKPj4KPj4gV2h5IGRvIHlvdSB3YW50IHRvIGVu YWJsZSAvIGRpc2FibGUgdGhlIGludGVycnJ1cHRzID8gVGhlIHNob3VsZCBiZQo+PiBhbHJlYWR5 IGhhbmRsZSBieSB0aGUgaG90cGx1ZyBmcmFtZXdvcmsgbm8gPwo+IAo+IFRoZSBwZXJDUFUgaW50 ZXJydXB0cyBhcmUgbm90IGVuYWJsZWQgYnkgZGVmYXVsdC4gV2UgaGF2ZSB0bwo+IGV4cGxpY2l0 bHkgZW5hYmxlL2Rpc2FibGUgcGVyQ1BVIGludGVycnVwdHMgaW4gQ1BVIGhvdHBsdWcgY2FsbGJh Y2tzLgo+IAoKSXNuJ3QgaXMgcG9zc2libGUgdG8gZG8gdGhhdCBpbiB0aGUgcHJvYmUvaW5pdCBm dW5jdGlvbiA/CgoKCi0tIAo8aHR0cDovL3d3dy5saW5hcm8ub3JnLz4gTGluYXJvLm9yZyDilIIg T3BlbiBzb3VyY2Ugc29mdHdhcmUgZm9yIEFSTSBTb0NzCgpGb2xsb3cgTGluYXJvOiAgPGh0dHA6 Ly93d3cuZmFjZWJvb2suY29tL3BhZ2VzL0xpbmFybz4gRmFjZWJvb2sgfAo8aHR0cDovL3R3aXR0 ZXIuY29tLyMhL2xpbmFyb29yZz4gVHdpdHRlciB8CjxodHRwOi8vd3d3LmxpbmFyby5vcmcvbGlu YXJvLWJsb2cvPiBCbG9nCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fXwpsaW51eC1yaXNjdiBtYWlsaW5nIGxpc3QKbGludXgtcmlzY3ZAbGlzdHMuaW5mcmFk ZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4 LXJpc2N2Cg==