From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:60412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSUPe-0004iW-Cg for qemu-devel@nongnu.org; Sun, 28 Oct 2012 11:04:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TSUPd-0005VB-FQ for qemu-devel@nongnu.org; Sun, 28 Oct 2012 11:04:30 -0400 Received: from mail-lb0-f173.google.com ([209.85.217.173]:38486) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSUPd-0005V1-8Q for qemu-devel@nongnu.org; Sun, 28 Oct 2012 11:04:29 -0400 Received: by mail-lb0-f173.google.com with SMTP id gj3so2486497lbb.4 for ; Sun, 28 Oct 2012 08:04:28 -0700 (PDT) From: Blue Swirl Date: Sun, 28 Oct 2012 15:03:51 +0000 Message-Id: <2134135d337e4836e51e5507d126eb837b593a79.1351436501.git.blauwirbel@gmail.com> In-Reply-To: References: In-Reply-To: References: Subject: [Qemu-devel] [PATCH 4/5] target-xtensa: avoid using cpu_single_env List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Max Filippov Pass around CPUState instead of using global cpu_single_env. Signed-off-by: Blue Swirl --- target-xtensa/translate.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 82e8ccc..3c03775 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -810,7 +810,7 @@ static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) return m; } -static void disas_xtensa_insn(DisasContext *dc) +static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { #define HAS_OPTION_BITS(opt) do { \ if (!option_bits_enabled(dc, opt)) { \ @@ -900,8 +900,8 @@ static void disas_xtensa_insn(DisasContext *dc) #define RSR_SR (b1) - uint8_t b0 = cpu_ldub_code(cpu_single_env, dc->pc); - uint8_t b1 = cpu_ldub_code(cpu_single_env, dc->pc + 1); + uint8_t b0 = cpu_ldub_code(env, dc->pc); + uint8_t b1 = cpu_ldub_code(env, dc->pc + 1); uint8_t b2 = 0; static const uint32_t B4CONST[] = { @@ -917,7 +917,7 @@ static void disas_xtensa_insn(DisasContext *dc) HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); } else { dc->next_pc = dc->pc + 3; - b2 = cpu_ldub_code(cpu_single_env, dc->pc + 2); + b2 = cpu_ldub_code(env, dc->pc + 2); } switch (OP0) { @@ -2931,7 +2931,7 @@ static void gen_intermediate_code_internal( gen_ibreak_check(env, &dc); } - disas_xtensa_insn(&dc); + disas_xtensa_insn(env, &dc); ++insn_count; if (dc.icount) { tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); -- 1.7.2.5