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* [PATCH 1/3] phy-sun4i-usb: Fix sun8i_r40_cfg
@ 2021-07-01  1:50 qianfanguijin
  2021-07-01  1:50 ` [PATCH 2/3] ARM: dts: sun8i: r40: Add usb_otg device node qianfanguijin
  2021-07-01  1:50 ` [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg qianfanguijin
  0 siblings, 2 replies; 14+ messages in thread
From: qianfanguijin @ 2021-07-01  1:50 UTC (permalink / raw)
  To: linux-sunxi; +Cc: mripard, wens, jernej.skrabec, qianfan Zhao

From: qianfan Zhao <qianfanguijin@163.com>

the r40 has the same configurations with a33, disable enable_pmu_unk1 and
phy0_dual_route feature.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 788dd5cdbb7d..8c4136e72947 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -935,8 +935,6 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
-	.phy0_dual_route = true,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
-- 
2.17.1



^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 2/3] ARM: dts: sun8i: r40: Add usb_otg device node
  2021-07-01  1:50 [PATCH 1/3] phy-sun4i-usb: Fix sun8i_r40_cfg qianfanguijin
@ 2021-07-01  1:50 ` qianfanguijin
  2021-07-01 14:29   ` Andre Przywara
  2021-07-01  1:50 ` [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg qianfanguijin
  1 sibling, 1 reply; 14+ messages in thread
From: qianfanguijin @ 2021-07-01  1:50 UTC (permalink / raw)
  To: linux-sunxi; +Cc: mripard, wens, jernej.skrabec, qianfan Zhao

From: qianfan Zhao <qianfanguijin@163.com>

R40's usb otg is compatibled with H3.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5ad3b9efd12..3edc849d39be 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -363,6 +363,20 @@
 			#size-cells = <0>;
 		};
 
+		usb_otg: usb@1c13000 {
+			compatible = "allwinner,sun8i-h3-musb";
+			reg = <0x01c13000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			dr_mode = "otg";
+			status = "disabled";
+		};
+
 		usbphy: phy@1c13400 {
 			compatible = "allwinner,sun8i-r40-usb-phy";
 			reg = <0x01c13400 0x14>,
-- 
2.17.1



^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-01  1:50 [PATCH 1/3] phy-sun4i-usb: Fix sun8i_r40_cfg qianfanguijin
  2021-07-01  1:50 ` [PATCH 2/3] ARM: dts: sun8i: r40: Add usb_otg device node qianfanguijin
@ 2021-07-01  1:50 ` qianfanguijin
  2021-07-01 14:37   ` Andre Przywara
  1 sibling, 1 reply; 14+ messages in thread
From: qianfanguijin @ 2021-07-01  1:50 UTC (permalink / raw)
  To: linux-sunxi; +Cc: mripard, wens, jernej.skrabec, qianfan Zhao

From: qianfan Zhao <qianfanguijin@163.com>

Enable it.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
---
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index a6a1087a0c9b..072535b383b5 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -43,6 +43,7 @@
 
 /dts-v1/;
 #include "sun8i-r40.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -299,6 +300,11 @@
 	regulator-name = "vdd1v2-sata";
 };
 
+&reg_usb0_vbus {
+	gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
+	status = "okay";
+};
+
 &tcon_tv0 {
 	status = "okay";
 };
@@ -328,7 +334,15 @@
 	};
 };
 
+&usb_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
 &usbphy {
+	usb0_id_det-gpios = <&pio 8 4 GPIO_ACTIVE_HIGH>; /* PI4 */
+	usb0_vbus_det-gpios = <&pio 8 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_vcc5v0>;
 	usb2_vbus-supply = <&reg_vcc5v0>;
 	status = "okay";
-- 
2.17.1



^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 2/3] ARM: dts: sun8i: r40: Add usb_otg device node
  2021-07-01  1:50 ` [PATCH 2/3] ARM: dts: sun8i: r40: Add usb_otg device node qianfanguijin
@ 2021-07-01 14:29   ` Andre Przywara
  0 siblings, 0 replies; 14+ messages in thread
From: Andre Przywara @ 2021-07-01 14:29 UTC (permalink / raw)
  To: qianfanguijin; +Cc: linux-sunxi, mripard, wens, jernej.skrabec

On Thu,  1 Jul 2021 09:50:08 +0800
qianfanguijin@163.com wrote:

Hi,

> From: qianfan Zhao <qianfanguijin@163.com>
> 
> R40's usb otg is compatibled with H3.
> 
> Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
> ---
>  arch/arm/boot/dts/sun8i-r40.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index d5ad3b9efd12..3edc849d39be 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -363,6 +363,20 @@
>  			#size-cells = <0>;
>  		};
>  
> +		usb_otg: usb@1c13000 {
> +			compatible = "allwinner,sun8i-h3-musb";

Please use a specific compatible string as well:
		compatible = "allwinner,sun8i-r40-musb",
			     "allwinner,sun8i-h3-musb";

The rest looks alright (base address, IRQ compared to the manual).

Thanks,
Andre



> +			reg = <0x01c13000 0x0400>;
> +			clocks = <&ccu CLK_BUS_OTG>;
> +			resets = <&ccu RST_BUS_OTG>;
> +			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "mc";
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			extcon = <&usbphy 0>;
> +			dr_mode = "otg";
> +			status = "disabled";
> +		};
> +
>  		usbphy: phy@1c13400 {
>  			compatible = "allwinner,sun8i-r40-usb-phy";
>  			reg = <0x01c13400 0x14>,


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-01  1:50 ` [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg qianfanguijin
@ 2021-07-01 14:37   ` Andre Przywara
  2021-07-01 14:47     ` Chen-Yu Tsai
  0 siblings, 1 reply; 14+ messages in thread
From: Andre Przywara @ 2021-07-01 14:37 UTC (permalink / raw)
  To: qianfanguijin; +Cc: linux-sunxi, mripard, wens, jernej.skrabec

On Thu,  1 Jul 2021 09:50:09 +0800
qianfanguijin@163.com wrote:

Hi,

> From: qianfan Zhao <qianfanguijin@163.com>
> 
> Enable it.
> 
> Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
> ---
>  arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> index a6a1087a0c9b..072535b383b5 100644
> --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> @@ -43,6 +43,7 @@
>  
>  /dts-v1/;
>  #include "sun8i-r40.dtsi"
> +#include "sunxi-common-regulators.dtsi"
>  
>  #include <dt-bindings/gpio/gpio.h>
>  
> @@ -299,6 +300,11 @@
>  	regulator-name = "vdd1v2-sata";
>  };
>  
> +&reg_usb0_vbus {
> +	gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
> +	status = "okay";
> +};

So there is the same USB0-DRVVBUS signal connected to this GPIO, but
also to the AXP's N_VBUSEN line.

Not sure if that means either of them can control the voltage?

> +
>  &tcon_tv0 {
>  	status = "okay";
>  };
> @@ -328,7 +334,15 @@
>  	};
>  };
>  
> +&usb_otg {
> +	dr_mode = "peripheral";

That should be "otg", since we have a working ID pin and can control
VBUS.

> +	status = "okay";
> +};
> +
>  &usbphy {
> +	usb0_id_det-gpios = <&pio 8 4 GPIO_ACTIVE_HIGH>; /* PI4 */
> +	usb0_vbus_det-gpios = <&pio 8 8 GPIO_ACTIVE_HIGH>; /* PH8 */

The comment should say PI8.

I don't have the board, but can at least confirm that the GPIO pins
(PI4, PI8 and PI13) match the schematic.

Cheers,
Andre

> +	usb0_vbus-supply = <&reg_usb0_vbus>;
>  	usb1_vbus-supply = <&reg_vcc5v0>;
>  	usb2_vbus-supply = <&reg_vcc5v0>;
>  	status = "okay";


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-01 14:37   ` Andre Przywara
@ 2021-07-01 14:47     ` Chen-Yu Tsai
  2021-07-02  2:46       ` qianfan
  0 siblings, 1 reply; 14+ messages in thread
From: Chen-Yu Tsai @ 2021-07-01 14:47 UTC (permalink / raw)
  To: Andre Przywara; +Cc: qianfanguijin, linux-sunxi, Maxime Ripard, Jernej Skrabec

On Thu, Jul 1, 2021 at 10:37 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Thu,  1 Jul 2021 09:50:09 +0800
> qianfanguijin@163.com wrote:
>
> Hi,
>
> > From: qianfan Zhao <qianfanguijin@163.com>
> >
> > Enable it.
> >
> > Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
> > ---
> >  arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > index a6a1087a0c9b..072535b383b5 100644
> > --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > @@ -43,6 +43,7 @@
> >
> >  /dts-v1/;
> >  #include "sun8i-r40.dtsi"
> > +#include "sunxi-common-regulators.dtsi"
> >
> >  #include <dt-bindings/gpio/gpio.h>
> >
> > @@ -299,6 +300,11 @@
> >       regulator-name = "vdd1v2-sata";
> >  };
> >
> > +&reg_usb0_vbus {
> > +     gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
> > +     status = "okay";
> > +};
>
> So there is the same USB0-DRVVBUS signal connected to this GPIO, but
> also to the AXP's N_VBUSEN line.
>
> Not sure if that means either of them can control the voltage?

It's better to use N_VBUSEN if that is connected. Since the PMIC
may have that pin already enabled, it can cause issues with VBUS
input not being correctly used.

ChenYu

> > +
> >  &tcon_tv0 {
> >       status = "okay";
> >  };
> > @@ -328,7 +334,15 @@
> >       };
> >  };
> >
> > +&usb_otg {
> > +     dr_mode = "peripheral";
>
> That should be "otg", since we have a working ID pin and can control
> VBUS.
>
> > +     status = "okay";
> > +};
> > +
> >  &usbphy {
> > +     usb0_id_det-gpios = <&pio 8 4 GPIO_ACTIVE_HIGH>; /* PI4 */
> > +     usb0_vbus_det-gpios = <&pio 8 8 GPIO_ACTIVE_HIGH>; /* PH8 */
>
> The comment should say PI8.
>
> I don't have the board, but can at least confirm that the GPIO pins
> (PI4, PI8 and PI13) match the schematic.
>
> Cheers,
> Andre
>
> > +     usb0_vbus-supply = <&reg_usb0_vbus>;
> >       usb1_vbus-supply = <&reg_vcc5v0>;
> >       usb2_vbus-supply = <&reg_vcc5v0>;
> >       status = "okay";
>

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-01 14:47     ` Chen-Yu Tsai
@ 2021-07-02  2:46       ` qianfan
  2021-07-02 12:06         ` Maxime Ripard
  0 siblings, 1 reply; 14+ messages in thread
From: qianfan @ 2021-07-02  2:46 UTC (permalink / raw)
  To: wens, Andre Przywara; +Cc: linux-sunxi, Maxime Ripard, Jernej Skrabec


在 2021/7/1 22:47, Chen-Yu Tsai 写道:
> On Thu, Jul 1, 2021 at 10:37 PM Andre Przywara <andre.przywara@arm.com> wrote:
>> On Thu,  1 Jul 2021 09:50:09 +0800
>> qianfanguijin@163.com wrote:
>>
>> Hi,
>>
>>> From: qianfan Zhao <qianfanguijin@163.com>
>>>
>>> Enable it.
>>>
>>> Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
>>> ---
>>>   arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
>>>   1 file changed, 14 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>>> index a6a1087a0c9b..072535b383b5 100644
>>> --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>>> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>>> @@ -43,6 +43,7 @@
>>>
>>>   /dts-v1/;
>>>   #include "sun8i-r40.dtsi"
>>> +#include "sunxi-common-regulators.dtsi"
>>>
>>>   #include <dt-bindings/gpio/gpio.h>
>>>
>>> @@ -299,6 +300,11 @@
>>>        regulator-name = "vdd1v2-sata";
>>>   };
>>>
>>> +&reg_usb0_vbus {
>>> +     gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
>>> +     status = "okay";
>>> +};
>> So there is the same USB0-DRVVBUS signal connected to this GPIO, but
>> also to the AXP's N_VBUSEN line.
>>
>> Not sure if that means either of them can control the voltage?
> It's better to use N_VBUSEN if that is connected. Since the PMIC
> may have that pin already enabled, it can cause issues with VBUS
> input not being correctly used.
>
> ChenYu

I had checked some boards in linux such as 
sun7i-a20-olinuxino-lime2.dts, they has the same design

that enable VBUS by using a gpio and then connect this gpio to PMIC.

there is a example:

./sun7i-a20-olinuxino-lime2.dts:&reg_usb0_vbus {
./sun7i-a20-olinuxino-lime2.dts-        gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
./sun7i-a20-olinuxino-lime2.dts-        status = "okay";
./sun7i-a20-olinuxino-lime2.dts-};

>>> +
>>>   &tcon_tv0 {
>>>        status = "okay";
>>>   };
>>> @@ -328,7 +334,15 @@
>>>        };
>>>   };
>>>
>>> +&usb_otg {
>>> +     dr_mode = "peripheral";
>> That should be "otg", since we have a working ID pin and can control
>> VBUS.
>>
>>> +     status = "okay";
>>> +};
>>> +
>>>   &usbphy {
>>> +     usb0_id_det-gpios = <&pio 8 4 GPIO_ACTIVE_HIGH>; /* PI4 */
>>> +     usb0_vbus_det-gpios = <&pio 8 8 GPIO_ACTIVE_HIGH>; /* PH8 */
>> The comment should say PI8.
>>
>> I don't have the board, but can at least confirm that the GPIO pins
>> (PI4, PI8 and PI13) match the schematic.
>>
>> Cheers,
>> Andre
>>
>>> +     usb0_vbus-supply = <&reg_usb0_vbus>;
>>>        usb1_vbus-supply = <&reg_vcc5v0>;
>>>        usb2_vbus-supply = <&reg_vcc5v0>;
>>>        status = "okay";


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-02  2:46       ` qianfan
@ 2021-07-02 12:06         ` Maxime Ripard
  2021-07-02 12:24           ` Andre Przywara
  0 siblings, 1 reply; 14+ messages in thread
From: Maxime Ripard @ 2021-07-02 12:06 UTC (permalink / raw)
  To: qianfan; +Cc: wens, Andre Przywara, linux-sunxi, Jernej Skrabec

[-- Attachment #1: Type: text/plain, Size: 2270 bytes --]

On Fri, Jul 02, 2021 at 10:46:20AM +0800, qianfan wrote:
> 
> 在 2021/7/1 22:47, Chen-Yu Tsai 写道:
> > On Thu, Jul 1, 2021 at 10:37 PM Andre Przywara <andre.przywara@arm.com> wrote:
> > > On Thu,  1 Jul 2021 09:50:09 +0800
> > > qianfanguijin@163.com wrote:
> > > 
> > > Hi,
> > > 
> > > > From: qianfan Zhao <qianfanguijin@163.com>
> > > > 
> > > > Enable it.
> > > > 
> > > > Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
> > > > ---
> > > >   arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
> > > >   1 file changed, 14 insertions(+)
> > > > 
> > > > diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > > > index a6a1087a0c9b..072535b383b5 100644
> > > > --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > > > +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > > > @@ -43,6 +43,7 @@
> > > > 
> > > >   /dts-v1/;
> > > >   #include "sun8i-r40.dtsi"
> > > > +#include "sunxi-common-regulators.dtsi"
> > > > 
> > > >   #include <dt-bindings/gpio/gpio.h>
> > > > 
> > > > @@ -299,6 +300,11 @@
> > > >        regulator-name = "vdd1v2-sata";
> > > >   };
> > > > 
> > > > +&reg_usb0_vbus {
> > > > +     gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
> > > > +     status = "okay";
> > > > +};
> > > So there is the same USB0-DRVVBUS signal connected to this GPIO, but
> > > also to the AXP's N_VBUSEN line.
> > > 
> > > Not sure if that means either of them can control the voltage?
> > It's better to use N_VBUSEN if that is connected. Since the PMIC
> > may have that pin already enabled, it can cause issues with VBUS
> > input not being correctly used.
>
> I had checked some boards in linux such as sun7i-a20-olinuxino-lime2.dts,
> they has the same design
> 
> that enable VBUS by using a gpio and then connect this gpio to PMIC.
> 
> there is a example:
> 
> ./sun7i-a20-olinuxino-lime2.dts:&reg_usb0_vbus {
> ./sun7i-a20-olinuxino-lime2.dts-        gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
> ./sun7i-a20-olinuxino-lime2.dts-        status = "okay";
> ./sun7i-a20-olinuxino-lime2.dts-};

IIRC, the AXP209 typically used with these boards doesn't have a
N_VBUSEN line

Maxime

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[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-02 12:06         ` Maxime Ripard
@ 2021-07-02 12:24           ` Andre Przywara
  2021-07-02 12:30             ` Chen-Yu Tsai
  0 siblings, 1 reply; 14+ messages in thread
From: Andre Przywara @ 2021-07-02 12:24 UTC (permalink / raw)
  To: Maxime Ripard; +Cc: qianfan, wens, linux-sunxi, Jernej Skrabec

On Fri, 2 Jul 2021 14:06:01 +0200
Maxime Ripard <maxime@cerno.tech> wrote:

Hi,

> On Fri, Jul 02, 2021 at 10:46:20AM +0800, qianfan wrote:
> > 
> > 在 2021/7/1 22:47, Chen-Yu Tsai 写道:  
> > > On Thu, Jul 1, 2021 at 10:37 PM Andre Przywara <andre.przywara@arm.com> wrote:  
> > > > On Thu,  1 Jul 2021 09:50:09 +0800
> > > > qianfanguijin@163.com wrote:
> > > > 
> > > > Hi,
> > > >   
> > > > > From: qianfan Zhao <qianfanguijin@163.com>
> > > > > 
> > > > > Enable it.
> > > > > 
> > > > > Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
> > > > > ---
> > > > >   arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
> > > > >   1 file changed, 14 insertions(+)
> > > > > 
> > > > > diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > > > > index a6a1087a0c9b..072535b383b5 100644
> > > > > --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > > > > +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > > > > @@ -43,6 +43,7 @@
> > > > > 
> > > > >   /dts-v1/;
> > > > >   #include "sun8i-r40.dtsi"
> > > > > +#include "sunxi-common-regulators.dtsi"
> > > > > 
> > > > >   #include <dt-bindings/gpio/gpio.h>
> > > > > 
> > > > > @@ -299,6 +300,11 @@
> > > > >        regulator-name = "vdd1v2-sata";
> > > > >   };
> > > > > 
> > > > > +&reg_usb0_vbus {
> > > > > +     gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
> > > > > +     status = "okay";
> > > > > +};  
> > > > So there is the same USB0-DRVVBUS signal connected to this GPIO, but
> > > > also to the AXP's N_VBUSEN line.
> > > > 
> > > > Not sure if that means either of them can control the voltage?  
> > > It's better to use N_VBUSEN if that is connected. Since the PMIC
> > > may have that pin already enabled, it can cause issues with VBUS
> > > input not being correctly used.  
> >
> > I had checked some boards in linux such as sun7i-a20-olinuxino-lime2.dts,
> > they has the same design
> > 
> > that enable VBUS by using a gpio and then connect this gpio to PMIC.
> > 
> > there is a example:
> > 
> > ./sun7i-a20-olinuxino-lime2.dts:&reg_usb0_vbus {
> > ./sun7i-a20-olinuxino-lime2.dts-        gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
> > ./sun7i-a20-olinuxino-lime2.dts-        status = "okay";
> > ./sun7i-a20-olinuxino-lime2.dts-};  
> 
> IIRC, the AXP209 typically used with these boards doesn't have a
> N_VBUSEN line

According to the Lime2 schematic and the AXP209 data sheet from the Wiki
it does have N_VBUSEN, from a quick glance with the usual
functionality. And the connection on the Lime2 looks indeed the same,
USB0_DRVVBUS connected to both the PMIC and a GPIO.
(Also the BPi-M2 Ultra has an AXP221 anyway.)

I would lean towards Chen-Yu's suggestion (use the PMIC).
It seems like my BPi M2 Berry uses the same layout, so I can do some
experiments later.

Cheers,
Andre

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-02 12:24           ` Andre Przywara
@ 2021-07-02 12:30             ` Chen-Yu Tsai
  2021-07-05  3:50               ` qianfan
  0 siblings, 1 reply; 14+ messages in thread
From: Chen-Yu Tsai @ 2021-07-02 12:30 UTC (permalink / raw)
  To: Andre Przywara; +Cc: Maxime Ripard, qianfan, linux-sunxi, Jernej Skrabec

On Fri, Jul 2, 2021 at 8:24 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Fri, 2 Jul 2021 14:06:01 +0200
> Maxime Ripard <maxime@cerno.tech> wrote:
>
> Hi,
>
> > On Fri, Jul 02, 2021 at 10:46:20AM +0800, qianfan wrote:
> > >
> > > 在 2021/7/1 22:47, Chen-Yu Tsai 写道:
> > > > On Thu, Jul 1, 2021 at 10:37 PM Andre Przywara <andre.przywara@arm.com> wrote:
> > > > > On Thu,  1 Jul 2021 09:50:09 +0800
> > > > > qianfanguijin@163.com wrote:
> > > > >
> > > > > Hi,
> > > > >
> > > > > > From: qianfan Zhao <qianfanguijin@163.com>
> > > > > >
> > > > > > Enable it.
> > > > > >
> > > > > > Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
> > > > > > ---
> > > > > >   arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
> > > > > >   1 file changed, 14 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > > > > > index a6a1087a0c9b..072535b383b5 100644
> > > > > > --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > > > > > +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> > > > > > @@ -43,6 +43,7 @@
> > > > > >
> > > > > >   /dts-v1/;
> > > > > >   #include "sun8i-r40.dtsi"
> > > > > > +#include "sunxi-common-regulators.dtsi"
> > > > > >
> > > > > >   #include <dt-bindings/gpio/gpio.h>
> > > > > >
> > > > > > @@ -299,6 +300,11 @@
> > > > > >        regulator-name = "vdd1v2-sata";
> > > > > >   };
> > > > > >
> > > > > > +&reg_usb0_vbus {
> > > > > > +     gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
> > > > > > +     status = "okay";
> > > > > > +};
> > > > > So there is the same USB0-DRVVBUS signal connected to this GPIO, but
> > > > > also to the AXP's N_VBUSEN line.
> > > > >
> > > > > Not sure if that means either of them can control the voltage?
> > > > It's better to use N_VBUSEN if that is connected. Since the PMIC
> > > > may have that pin already enabled, it can cause issues with VBUS
> > > > input not being correctly used.
> > >
> > > I had checked some boards in linux such as sun7i-a20-olinuxino-lime2.dts,
> > > they has the same design
> > >
> > > that enable VBUS by using a gpio and then connect this gpio to PMIC.
> > >
> > > there is a example:
> > >
> > > ./sun7i-a20-olinuxino-lime2.dts:&reg_usb0_vbus {
> > > ./sun7i-a20-olinuxino-lime2.dts-        gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
> > > ./sun7i-a20-olinuxino-lime2.dts-        status = "okay";
> > > ./sun7i-a20-olinuxino-lime2.dts-};
> >
> > IIRC, the AXP209 typically used with these boards doesn't have a
> > N_VBUSEN line
>
> According to the Lime2 schematic and the AXP209 data sheet from the Wiki
> it does have N_VBUSEN, from a quick glance with the usual
> functionality. And the connection on the Lime2 looks indeed the same,
> USB0_DRVVBUS connected to both the PMIC and a GPIO.
> (Also the BPi-M2 Ultra has an AXP221 anyway.)

The difference is that the N_VBUSEN pin on the AXP221 can be used as an
output, while on the AXP209 it is strictly an input. And U-Boot tends
to leave pins it has used in whatever state last used so ideally we
need to coordinate both to use the same method. Otherwise you might
end up with N_VBUSEN always driving DRVVBUS high or low, and the GPIO
on the SoC not having any effect. Ideally we need some way to reset
the state of the pins to high-Z.

ChenYu

> I would lean towards Chen-Yu's suggestion (use the PMIC).
> It seems like my BPi M2 Berry uses the same layout, so I can do some
> experiments later.

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-02 12:30             ` Chen-Yu Tsai
@ 2021-07-05  3:50               ` qianfan
  2021-07-05  6:20                 ` Chen-Yu Tsai
  0 siblings, 1 reply; 14+ messages in thread
From: qianfan @ 2021-07-05  3:50 UTC (permalink / raw)
  To: wens, Andre Przywara; +Cc: Maxime Ripard, linux-sunxi, Jernej Skrabec


在 2021/7/2 20:30, Chen-Yu Tsai 写道:
> On Fri, Jul 2, 2021 at 8:24 PM Andre Przywara <andre.przywara@arm.com> wrote:
>> On Fri, 2 Jul 2021 14:06:01 +0200
>> Maxime Ripard <maxime@cerno.tech> wrote:
>>
>> Hi,
>>
>>> On Fri, Jul 02, 2021 at 10:46:20AM +0800, qianfan wrote:
>>>> 在 2021/7/1 22:47, Chen-Yu Tsai 写道:
>>>>> On Thu, Jul 1, 2021 at 10:37 PM Andre Przywara <andre.przywara@arm.com> wrote:
>>>>>> On Thu,  1 Jul 2021 09:50:09 +0800
>>>>>> qianfanguijin@163.com wrote:
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>>> From: qianfan Zhao <qianfanguijin@163.com>
>>>>>>>
>>>>>>> Enable it.
>>>>>>>
>>>>>>> Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
>>>>>>> ---
>>>>>>>    arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
>>>>>>>    1 file changed, 14 insertions(+)
>>>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>>>>>>> index a6a1087a0c9b..072535b383b5 100644
>>>>>>> --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>>>>>>> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>>>>>>> @@ -43,6 +43,7 @@
>>>>>>>
>>>>>>>    /dts-v1/;
>>>>>>>    #include "sun8i-r40.dtsi"
>>>>>>> +#include "sunxi-common-regulators.dtsi"
>>>>>>>
>>>>>>>    #include <dt-bindings/gpio/gpio.h>
>>>>>>>
>>>>>>> @@ -299,6 +300,11 @@
>>>>>>>         regulator-name = "vdd1v2-sata";
>>>>>>>    };
>>>>>>>
>>>>>>> +&reg_usb0_vbus {
>>>>>>> +     gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
>>>>>>> +     status = "okay";
>>>>>>> +};
>>>>>> So there is the same USB0-DRVVBUS signal connected to this GPIO, but
>>>>>> also to the AXP's N_VBUSEN line.
>>>>>>
>>>>>> Not sure if that means either of them can control the voltage?
>>>>> It's better to use N_VBUSEN if that is connected. Since the PMIC
>>>>> may have that pin already enabled, it can cause issues with VBUS
>>>>> input not being correctly used.
>>>> I had checked some boards in linux such as sun7i-a20-olinuxino-lime2.dts,
>>>> they has the same design
>>>>
>>>> that enable VBUS by using a gpio and then connect this gpio to PMIC.
>>>>
>>>> there is a example:
>>>>
>>>> ./sun7i-a20-olinuxino-lime2.dts:&reg_usb0_vbus {
>>>> ./sun7i-a20-olinuxino-lime2.dts-        gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
>>>> ./sun7i-a20-olinuxino-lime2.dts-        status = "okay";
>>>> ./sun7i-a20-olinuxino-lime2.dts-};
>>> IIRC, the AXP209 typically used with these boards doesn't have a
>>> N_VBUSEN line
>> According to the Lime2 schematic and the AXP209 data sheet from the Wiki
>> it does have N_VBUSEN, from a quick glance with the usual
>> functionality. And the connection on the Lime2 looks indeed the same,
>> USB0_DRVVBUS connected to both the PMIC and a GPIO.
>> (Also the BPi-M2 Ultra has an AXP221 anyway.)
> The difference is that the N_VBUSEN pin on the AXP221 can be used as an
> output, while on the AXP209 it is strictly an input. And U-Boot tends
> to leave pins it has used in whatever state last used so ideally we
> need to coordinate both to use the same method. Otherwise you might
> end up with N_VBUSEN always driving DRVVBUS high or low, and the GPIO
> on the SoC not having any effect. Ideally we need some way to reset
> the state of the pins to high-Z.
>
> ChenYu

I had changed the dts to control VBUS by using PMIC, but I had a 
question: what's the perpose of

the gpio?

>
>> I would lean towards Chen-Yu's suggestion (use the PMIC).
>> It seems like my BPi M2 Berry uses the same layout, so I can do some
>> experiments later.


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-05  3:50               ` qianfan
@ 2021-07-05  6:20                 ` Chen-Yu Tsai
  2021-07-05  6:29                   ` qianfan
  0 siblings, 1 reply; 14+ messages in thread
From: Chen-Yu Tsai @ 2021-07-05  6:20 UTC (permalink / raw)
  To: qianfan; +Cc: Andre Przywara, Maxime Ripard, linux-sunxi, Jernej Skrabec

On Mon, Jul 5, 2021 at 11:51 AM qianfan <qianfanguijin@163.com> wrote:
> 在 2021/7/2 20:30, Chen-Yu Tsai 写道:
> > On Fri, Jul 2, 2021 at 8:24 PM Andre Przywara <andre.przywara@arm.com> wrote:
> >> On Fri, 2 Jul 2021 14:06:01 +0200
> >> Maxime Ripard <maxime@cerno.tech> wrote:
> >>
> >> Hi,
> >>
> >>> On Fri, Jul 02, 2021 at 10:46:20AM +0800, qianfan wrote:
> >>>> 在 2021/7/1 22:47, Chen-Yu Tsai 写道:
> >>>>> On Thu, Jul 1, 2021 at 10:37 PM Andre Przywara <andre.przywara@arm.com> wrote:
> >>>>>> On Thu,  1 Jul 2021 09:50:09 +0800
> >>>>>> qianfanguijin@163.com wrote:
> >>>>>>
> >>>>>> Hi,
> >>>>>>
> >>>>>>> From: qianfan Zhao <qianfanguijin@163.com>
> >>>>>>>
> >>>>>>> Enable it.
> >>>>>>>
> >>>>>>> Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
> >>>>>>> ---
> >>>>>>>    arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
> >>>>>>>    1 file changed, 14 insertions(+)
> >>>>>>>
> >>>>>>> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> >>>>>>> index a6a1087a0c9b..072535b383b5 100644
> >>>>>>> --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> >>>>>>> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> >>>>>>> @@ -43,6 +43,7 @@
> >>>>>>>
> >>>>>>>    /dts-v1/;
> >>>>>>>    #include "sun8i-r40.dtsi"
> >>>>>>> +#include "sunxi-common-regulators.dtsi"
> >>>>>>>
> >>>>>>>    #include <dt-bindings/gpio/gpio.h>
> >>>>>>>
> >>>>>>> @@ -299,6 +300,11 @@
> >>>>>>>         regulator-name = "vdd1v2-sata";
> >>>>>>>    };
> >>>>>>>
> >>>>>>> +&reg_usb0_vbus {
> >>>>>>> +     gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
> >>>>>>> +     status = "okay";
> >>>>>>> +};
> >>>>>> So there is the same USB0-DRVVBUS signal connected to this GPIO, but
> >>>>>> also to the AXP's N_VBUSEN line.
> >>>>>>
> >>>>>> Not sure if that means either of them can control the voltage?
> >>>>> It's better to use N_VBUSEN if that is connected. Since the PMIC
> >>>>> may have that pin already enabled, it can cause issues with VBUS
> >>>>> input not being correctly used.
> >>>> I had checked some boards in linux such as sun7i-a20-olinuxino-lime2.dts,
> >>>> they has the same design
> >>>>
> >>>> that enable VBUS by using a gpio and then connect this gpio to PMIC.
> >>>>
> >>>> there is a example:
> >>>>
> >>>> ./sun7i-a20-olinuxino-lime2.dts:&reg_usb0_vbus {
> >>>> ./sun7i-a20-olinuxino-lime2.dts-        gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
> >>>> ./sun7i-a20-olinuxino-lime2.dts-        status = "okay";
> >>>> ./sun7i-a20-olinuxino-lime2.dts-};
> >>> IIRC, the AXP209 typically used with these boards doesn't have a
> >>> N_VBUSEN line
> >> According to the Lime2 schematic and the AXP209 data sheet from the Wiki
> >> it does have N_VBUSEN, from a quick glance with the usual
> >> functionality. And the connection on the Lime2 looks indeed the same,
> >> USB0_DRVVBUS connected to both the PMIC and a GPIO.
> >> (Also the BPi-M2 Ultra has an AXP221 anyway.)
> > The difference is that the N_VBUSEN pin on the AXP221 can be used as an
> > output, while on the AXP209 it is strictly an input. And U-Boot tends
> > to leave pins it has used in whatever state last used so ideally we
> > need to coordinate both to use the same method. Otherwise you might
> > end up with N_VBUSEN always driving DRVVBUS high or low, and the GPIO
> > on the SoC not having any effect. Ideally we need some way to reset
> > the state of the pins to high-Z.
> >
> > ChenYu
>
> I had changed the dts to control VBUS by using PMIC, but I had a
> question: what's the perpose of
>
> the gpio?

Which GPIO? You mean the one on the SoC wired to N_VBUSEN and DRVVBUS?
Or N_VBUSEN itself?

ChenYu

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-05  6:20                 ` Chen-Yu Tsai
@ 2021-07-05  6:29                   ` qianfan
  2021-07-05 14:20                     ` Chen-Yu Tsai
  0 siblings, 1 reply; 14+ messages in thread
From: qianfan @ 2021-07-05  6:29 UTC (permalink / raw)
  To: wens; +Cc: Andre Przywara, Maxime Ripard, linux-sunxi, Jernej Skrabec


在 2021/7/5 14:20, Chen-Yu Tsai 写道:
> On Mon, Jul 5, 2021 at 11:51 AM qianfan <qianfanguijin@163.com> wrote:
>> 在 2021/7/2 20:30, Chen-Yu Tsai 写道:
>>> On Fri, Jul 2, 2021 at 8:24 PM Andre Przywara <andre.przywara@arm.com> wrote:
>>>> On Fri, 2 Jul 2021 14:06:01 +0200
>>>> Maxime Ripard <maxime@cerno.tech> wrote:
>>>>
>>>> Hi,
>>>>
>>>>> On Fri, Jul 02, 2021 at 10:46:20AM +0800, qianfan wrote:
>>>>>> 在 2021/7/1 22:47, Chen-Yu Tsai 写道:
>>>>>>> On Thu, Jul 1, 2021 at 10:37 PM Andre Przywara <andre.przywara@arm.com> wrote:
>>>>>>>> On Thu,  1 Jul 2021 09:50:09 +0800
>>>>>>>> qianfanguijin@163.com wrote:
>>>>>>>>
>>>>>>>> Hi,
>>>>>>>>
>>>>>>>>> From: qianfan Zhao <qianfanguijin@163.com>
>>>>>>>>>
>>>>>>>>> Enable it.
>>>>>>>>>
>>>>>>>>> Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
>>>>>>>>> ---
>>>>>>>>>     arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
>>>>>>>>>     1 file changed, 14 insertions(+)
>>>>>>>>>
>>>>>>>>> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>>>>>>>>> index a6a1087a0c9b..072535b383b5 100644
>>>>>>>>> --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>>>>>>>>> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>>>>>>>>> @@ -43,6 +43,7 @@
>>>>>>>>>
>>>>>>>>>     /dts-v1/;
>>>>>>>>>     #include "sun8i-r40.dtsi"
>>>>>>>>> +#include "sunxi-common-regulators.dtsi"
>>>>>>>>>
>>>>>>>>>     #include <dt-bindings/gpio/gpio.h>
>>>>>>>>>
>>>>>>>>> @@ -299,6 +300,11 @@
>>>>>>>>>          regulator-name = "vdd1v2-sata";
>>>>>>>>>     };
>>>>>>>>>
>>>>>>>>> +&reg_usb0_vbus {
>>>>>>>>> +     gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
>>>>>>>>> +     status = "okay";
>>>>>>>>> +};
>>>>>>>> So there is the same USB0-DRVVBUS signal connected to this GPIO, but
>>>>>>>> also to the AXP's N_VBUSEN line.
>>>>>>>>
>>>>>>>> Not sure if that means either of them can control the voltage?
>>>>>>> It's better to use N_VBUSEN if that is connected. Since the PMIC
>>>>>>> may have that pin already enabled, it can cause issues with VBUS
>>>>>>> input not being correctly used.
>>>>>> I had checked some boards in linux such as sun7i-a20-olinuxino-lime2.dts,
>>>>>> they has the same design
>>>>>>
>>>>>> that enable VBUS by using a gpio and then connect this gpio to PMIC.
>>>>>>
>>>>>> there is a example:
>>>>>>
>>>>>> ./sun7i-a20-olinuxino-lime2.dts:&reg_usb0_vbus {
>>>>>> ./sun7i-a20-olinuxino-lime2.dts-        gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
>>>>>> ./sun7i-a20-olinuxino-lime2.dts-        status = "okay";
>>>>>> ./sun7i-a20-olinuxino-lime2.dts-};
>>>>> IIRC, the AXP209 typically used with these boards doesn't have a
>>>>> N_VBUSEN line
>>>> According to the Lime2 schematic and the AXP209 data sheet from the Wiki
>>>> it does have N_VBUSEN, from a quick glance with the usual
>>>> functionality. And the connection on the Lime2 looks indeed the same,
>>>> USB0_DRVVBUS connected to both the PMIC and a GPIO.
>>>> (Also the BPi-M2 Ultra has an AXP221 anyway.)
>>> The difference is that the N_VBUSEN pin on the AXP221 can be used as an
>>> output, while on the AXP209 it is strictly an input. And U-Boot tends
>>> to leave pins it has used in whatever state last used so ideally we
>>> need to coordinate both to use the same method. Otherwise you might
>>> end up with N_VBUSEN always driving DRVVBUS high or low, and the GPIO
>>> on the SoC not having any effect. Ideally we need some way to reset
>>> the state of the pins to high-Z.
>>>
>>> ChenYu
>> I had changed the dts to control VBUS by using PMIC, but I had a
>> question: what's the perpose of
>>
>> the gpio?
> Which GPIO? You mean the one on the SoC wired to N_VBUSEN and DRVVBUS?
> Or N_VBUSEN itself?
I means USB0-DRVVBUS(PI13) on bpi m2u. We can control VBUS by PMIC, and 
PI13 seems is a redundant design.
>
> ChenYu


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg
  2021-07-05  6:29                   ` qianfan
@ 2021-07-05 14:20                     ` Chen-Yu Tsai
  0 siblings, 0 replies; 14+ messages in thread
From: Chen-Yu Tsai @ 2021-07-05 14:20 UTC (permalink / raw)
  To: qianfan; +Cc: Andre Przywara, Maxime Ripard, linux-sunxi, Jernej Skrabec

On Mon, Jul 5, 2021 at 2:30 PM qianfan <qianfanguijin@163.com> wrote:
> 在 2021/7/5 14:20, Chen-Yu Tsai 写道:
> > On Mon, Jul 5, 2021 at 11:51 AM qianfan <qianfanguijin@163.com> wrote:
> >> 在 2021/7/2 20:30, Chen-Yu Tsai 写道:
> >>> On Fri, Jul 2, 2021 at 8:24 PM Andre Przywara <andre.przywara@arm.com> wrote:
> >>>> On Fri, 2 Jul 2021 14:06:01 +0200
> >>>> Maxime Ripard <maxime@cerno.tech> wrote:
> >>>>
> >>>> Hi,
> >>>>
> >>>>> On Fri, Jul 02, 2021 at 10:46:20AM +0800, qianfan wrote:
> >>>>>> 在 2021/7/1 22:47, Chen-Yu Tsai 写道:
> >>>>>>> On Thu, Jul 1, 2021 at 10:37 PM Andre Przywara <andre.przywara@arm.com> wrote:
> >>>>>>>> On Thu,  1 Jul 2021 09:50:09 +0800
> >>>>>>>> qianfanguijin@163.com wrote:
> >>>>>>>>
> >>>>>>>> Hi,
> >>>>>>>>
> >>>>>>>>> From: qianfan Zhao <qianfanguijin@163.com>
> >>>>>>>>>
> >>>>>>>>> Enable it.
> >>>>>>>>>
> >>>>>>>>> Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
> >>>>>>>>> ---
> >>>>>>>>>     arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
> >>>>>>>>>     1 file changed, 14 insertions(+)
> >>>>>>>>>
> >>>>>>>>> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> >>>>>>>>> index a6a1087a0c9b..072535b383b5 100644
> >>>>>>>>> --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> >>>>>>>>> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> >>>>>>>>> @@ -43,6 +43,7 @@
> >>>>>>>>>
> >>>>>>>>>     /dts-v1/;
> >>>>>>>>>     #include "sun8i-r40.dtsi"
> >>>>>>>>> +#include "sunxi-common-regulators.dtsi"
> >>>>>>>>>
> >>>>>>>>>     #include <dt-bindings/gpio/gpio.h>
> >>>>>>>>>
> >>>>>>>>> @@ -299,6 +300,11 @@
> >>>>>>>>>          regulator-name = "vdd1v2-sata";
> >>>>>>>>>     };
> >>>>>>>>>
> >>>>>>>>> +&reg_usb0_vbus {
> >>>>>>>>> +     gpio = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */
> >>>>>>>>> +     status = "okay";
> >>>>>>>>> +};
> >>>>>>>> So there is the same USB0-DRVVBUS signal connected to this GPIO, but
> >>>>>>>> also to the AXP's N_VBUSEN line.
> >>>>>>>>
> >>>>>>>> Not sure if that means either of them can control the voltage?
> >>>>>>> It's better to use N_VBUSEN if that is connected. Since the PMIC
> >>>>>>> may have that pin already enabled, it can cause issues with VBUS
> >>>>>>> input not being correctly used.
> >>>>>> I had checked some boards in linux such as sun7i-a20-olinuxino-lime2.dts,
> >>>>>> they has the same design
> >>>>>>
> >>>>>> that enable VBUS by using a gpio and then connect this gpio to PMIC.
> >>>>>>
> >>>>>> there is a example:
> >>>>>>
> >>>>>> ./sun7i-a20-olinuxino-lime2.dts:&reg_usb0_vbus {
> >>>>>> ./sun7i-a20-olinuxino-lime2.dts-        gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
> >>>>>> ./sun7i-a20-olinuxino-lime2.dts-        status = "okay";
> >>>>>> ./sun7i-a20-olinuxino-lime2.dts-};
> >>>>> IIRC, the AXP209 typically used with these boards doesn't have a
> >>>>> N_VBUSEN line
> >>>> According to the Lime2 schematic and the AXP209 data sheet from the Wiki
> >>>> it does have N_VBUSEN, from a quick glance with the usual
> >>>> functionality. And the connection on the Lime2 looks indeed the same,
> >>>> USB0_DRVVBUS connected to both the PMIC and a GPIO.
> >>>> (Also the BPi-M2 Ultra has an AXP221 anyway.)
> >>> The difference is that the N_VBUSEN pin on the AXP221 can be used as an
> >>> output, while on the AXP209 it is strictly an input. And U-Boot tends
> >>> to leave pins it has used in whatever state last used so ideally we
> >>> need to coordinate both to use the same method. Otherwise you might
> >>> end up with N_VBUSEN always driving DRVVBUS high or low, and the GPIO
> >>> on the SoC not having any effect. Ideally we need some way to reset
> >>> the state of the pins to high-Z.
> >>>
> >>> ChenYu
> >> I had changed the dts to control VBUS by using PMIC, but I had a
> >> question: what's the perpose of
> >>
> >> the gpio?
> > Which GPIO? You mean the one on the SoC wired to N_VBUSEN and DRVVBUS?
> > Or N_VBUSEN itself?
> I means USB0-DRVVBUS(PI13) on bpi m2u. We can control VBUS by PMIC, and
> PI13 seems is a redundant design.

Well, that depends on if you want the PMIC to be the component in control.
If you want the SoC to be in control, then the N_VBUSEN pin could be put
in its input mode instead.


ChenYu

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2021-07-05 14:21 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-01  1:50 [PATCH 1/3] phy-sun4i-usb: Fix sun8i_r40_cfg qianfanguijin
2021-07-01  1:50 ` [PATCH 2/3] ARM: dts: sun8i: r40: Add usb_otg device node qianfanguijin
2021-07-01 14:29   ` Andre Przywara
2021-07-01  1:50 ` [PATCH 3/3] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable usb_otg qianfanguijin
2021-07-01 14:37   ` Andre Przywara
2021-07-01 14:47     ` Chen-Yu Tsai
2021-07-02  2:46       ` qianfan
2021-07-02 12:06         ` Maxime Ripard
2021-07-02 12:24           ` Andre Przywara
2021-07-02 12:30             ` Chen-Yu Tsai
2021-07-05  3:50               ` qianfan
2021-07-05  6:20                 ` Chen-Yu Tsai
2021-07-05  6:29                   ` qianfan
2021-07-05 14:20                     ` Chen-Yu Tsai

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