From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by smtp.lore.kernel.org (Postfix) with ESMTP id D39B9C433EF for ; Tue, 29 Mar 2022 18:51:47 +0000 (UTC) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BB03D40691; Tue, 29 Mar 2022 20:51:46 +0200 (CEST) Received: from wout5-smtp.messagingengine.com (wout5-smtp.messagingengine.com [64.147.123.21]) by mails.dpdk.org (Postfix) with ESMTP id 4C0D640141 for ; Tue, 29 Mar 2022 20:51:45 +0200 (CEST) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id AD9103201F88; Tue, 29 Mar 2022 14:51:43 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Tue, 29 Mar 2022 14:51:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; bh=IwmYX1hxVIODPe dAlGslTEnASA/jmxpkRgjsHk0u4H4=; b=tCx7498saDw48yoeWbVU29sJ70ANcu UlyEOVRUmDqahFxzJFTfBb30npqbxib46BPVUcs4FGusryKPQWjxDmirHx9fRc6t 7p/KVefhfSO+cQxPSGPfe/kHpUYFljNO4BG0IWF5Pz1FefczzHUXIYDF2VavBX1t tPaMawLMTpyDGvI6qBwKsfZdchwSMMtiO3lSVaY9qixHkaazQ9cWjrASem+1Wr/q 1xSmOapGTF9SCSHAl2K3UfXxYFTklRJMT6wrVg4bt6/TcxToha4SHrdyxmFqLHKn 3Cp6HShrmyQ7/K0JNPQOsv0G1zlbdMkwTTmo47srkQjcL8k5kpUUe36g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; bh=IwmYX1hxVIODPedAlGslTEnASA/jmxpkRgjsHk0u4 H4=; b=U09Pkocje38A4/twiHMycSxogwFFLozxYgQZELtP46Gp4xUat7v4/CgKo 4y2glT7PJ5Mqxs46zhK850yE79xERbyr+dbnddMpcRx8bpwMYNrA97Xz1UhCTMH8 VGYlZOPW4dAcZXtOY7/MVADq8ktgqGluENi8TyCO0S1K4yXsEl+5x8SO2dtPOSr+ 3Vx/YhTL02gwgNhYumXkTAajq6S+p631OITEDSXOL0t3hJILYPfXHKKzsFtsFJfz UYAcC3E5J8oM/7HHyxFpoLZXFUUrbxNtqPxXvPH287ypxWy8KKyniA82y6ymQgir eo1BUZUGxYW4DBf95RgOaFLLqYqAA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvvddrudeitddguddtgecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvffufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhm rghsucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenuc ggtffrrghtthgvrhhnpedugefgvdefudfftdefgeelgffhueekgfffhfeujedtteeutdej ueeiiedvffegheenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehthhhomhgrshesmhhonhhjrghlohhnrdhnvght X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 29 Mar 2022 14:51:42 -0400 (EDT) From: Thomas Monjalon To: "Chautru, Nicolas" Cc: "Mcnamara, John" , "dev@dpdk.org" , "Devlin, Michelle" Subject: Re: Intel roadmap for 22.07 Date: Tue, 29 Mar 2022 20:51:40 +0200 Message-ID: <2143173.ZfL8zNpBrT@thomas> In-Reply-To: References: <3106786.vfdyTQepKt@thomas> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 29/03/2022 17:13, Chautru, Nicolas: > Hi Thomas, > > The ACC101 PMD is to support a new silicon being PRQ this year by Intel. Note this is not a FPGA but an actual ASIC. > There is some similarity with ACC100 but still a brand new silicon, new features, number of silicon bug fixes, different number of engines, different performance and hence a separate PMD. > Let me know I unclear Are you sure you tried hard to manage them with a common code? Last time we asked such question, it was for DLB, and it became clear later that it should be the same code, otherwise you fix bugs two times, etc. I understand it is a new silicon, but do you know the net driver mlx5 is the same for various hardware of the last 10 years? > From: Thomas Monjalon > > 24/03/2022 09:32, Mcnamara, John: > > > * DLB allow assignment of SW/HW credit quanta assignment on port usage > > > hint > > > * DLB allow dlb2 eventdev apps to use specific COS on per port basis > > > * DLB add support for DLB 2.5 QE weight hardware feature > > > > DLB and DLB2 were introduced as different but very similar drivers, and they > > got eventually merged. > > > > > * bbdev new PMD for Intel ACC101 device > > > > Is it really going to be a separate driver of ACC100?