From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936269AbcCQQnI (ORCPT ); Thu, 17 Mar 2016 12:43:08 -0400 Received: from galahad.ideasonboard.com ([185.26.127.97]:33757 "EHLO galahad.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936159AbcCQQnG convert rfc822-to-8bit (ORCPT ); Thu, 17 Mar 2016 12:43:06 -0400 From: Laurent Pinchart To: Sebastian Reichel Cc: Tony Lindgren , Aaro Koskinen , Tomi Valkeinen , David Airlie , linux-omap@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 02/23] ARM: dts: n950: add display support Date: Thu, 17 Mar 2016 14:14:26 +0200 Message-ID: <21766689.NesyW3QHk4@avalon> User-Agent: KMail/4.14.8 (Linux/4.1.15-gentoo-r1; KDE/4.14.8; x86_64; ; ) In-Reply-To: <1457455195-1938-3-git-send-email-sre@kernel.org> References: <1457455195-1938-1-git-send-email-sre@kernel.org> <1457455195-1938-3-git-send-email-sre@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sebastian, Thank you for the patch. On Tuesday 08 March 2016 17:39:34 Sebastian Reichel wrote: > Signed-off-By: Sebastian Reichel > --- > arch/arm/boot/dts/omap3-n950.dts | 71 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 71 insertions(+) > > diff --git a/arch/arm/boot/dts/omap3-n950.dts > b/arch/arm/boot/dts/omap3-n950.dts index 0885b34d5d7d..41b8fb585272 100644 > --- a/arch/arm/boot/dts/omap3-n950.dts > +++ b/arch/arm/boot/dts/omap3-n950.dts > @@ -17,6 +17,26 @@ > compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3"; > }; > > +&omap3_pmx_core { > + dsi_pins: pinmux_dsi_pins { > + pinctrl-single,pins = < > + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - > data0+ */ > + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - > data0- */ > + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE1) /* dsi_dx1 - > clk+ */ > + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE1) /* dsi_dy1 - > clk- */ > + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE1) /* dsi_dx2 - > data1+ */ > + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE1) /* dsi_dy2 - > data1- */ > + >; > + }; > + > + display_pins: pinmux_display_pins { > + pinctrl-single,pins = < > + OMAP3_CORE1_IOPAD(0x20ca, PIN_INPUT | MUX_MODE4) /* gpio 62 - > display te */ > + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 - > display reset */ > + >; > + }; > +}; > + > &i2c2 { > smia_1: camera@10 { > compatible = "nokia,smia"; > @@ -53,3 +73,54 @@ > }; > }; > }; > + > +&dss { > + status = "ok"; > + > + vdda_video-supply = <&vdac>; > +}; > + > +&dsi { > + status = "ok"; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&dsi_pins>; > + > + vdd-supply = <&vpll2>; > + > + port { > + dsi_out_ep: endpoint { > + remote-endpoint = <&lcd0_in>; > + lanes = <2 3 0 1 4 5>; > + }; > + }; > + > + lcd0: display { > + compatible = "nokia,himalaya", "panel-dsi-cm"; > + label = "lcd0"; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&display_pins>; > + > + vpnl-supply = <&vmmc2>; > + vddi-supply = <&vio>; > + > + reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ > + te-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; /* 62 */ > + > + has-dsi-backlight; > + > + /* panel is 480x464 with top and bottom 5 lines not visible */ I assume you mean 480x864 ? > + /* physical dimensions: 48960µm x 88128µm */ > + resolution-x = <480>; > + resolution-y = <854>; > + offset-x = <0>; > + offset-y = <5>; > + > + port { > + lcd0_in: endpoint { > + remote-endpoint = <&dsi_out_ep>; > + }; > + }; > + }; > +}; -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH 02/23] ARM: dts: n950: add display support Date: Thu, 17 Mar 2016 14:14:26 +0200 Message-ID: <21766689.NesyW3QHk4@avalon> References: <1457455195-1938-1-git-send-email-sre@kernel.org> <1457455195-1938-3-git-send-email-sre@kernel.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1457455195-1938-3-git-send-email-sre@kernel.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Sebastian Reichel Cc: Aaro Koskinen , Tony Lindgren , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Tomi Valkeinen , linux-omap@vger.kernel.org List-Id: linux-omap@vger.kernel.org SGkgU2ViYXN0aWFuLAoKVGhhbmsgeW91IGZvciB0aGUgcGF0Y2guCgpPbiBUdWVzZGF5IDA4IE1h cmNoIDIwMTYgMTc6Mzk6MzQgU2ViYXN0aWFuIFJlaWNoZWwgd3JvdGU6Cj4gU2lnbmVkLW9mZi1C eTogU2ViYXN0aWFuIFJlaWNoZWwgPHNyZUBrZXJuZWwub3JnPgo+IC0tLQo+ICBhcmNoL2FybS9i b290L2R0cy9vbWFwMy1uOTUwLmR0cyB8IDcxICsrKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKysKPiAgMSBmaWxlIGNoYW5nZWQsIDcxIGluc2VydGlvbnMoKykKPiAKPiBkaWZmIC0t Z2l0IGEvYXJjaC9hcm0vYm9vdC9kdHMvb21hcDMtbjk1MC5kdHMKPiBiL2FyY2gvYXJtL2Jvb3Qv ZHRzL29tYXAzLW45NTAuZHRzIGluZGV4IDA4ODViMzRkNWQ3ZC4uNDFiOGZiNTg1MjcyIDEwMDY0 NAo+IC0tLSBhL2FyY2gvYXJtL2Jvb3QvZHRzL29tYXAzLW45NTAuZHRzCj4gKysrIGIvYXJjaC9h cm0vYm9vdC9kdHMvb21hcDMtbjk1MC5kdHMKPiBAQCAtMTcsNiArMTcsMjYgQEAKPiAgCWNvbXBh dGlibGUgPSAibm9raWEsb21hcDMtbjk1MCIsICJ0aSxvbWFwMzZ4eCIsICJ0aSxvbWFwMyI7Cj4g IH07Cj4gCj4gKyZvbWFwM19wbXhfY29yZSB7Cj4gKwlkc2lfcGluczogcGlubXV4X2RzaV9waW5z IHsKPiArCQlwaW5jdHJsLXNpbmdsZSxwaW5zID0gPAo+ICsJCQlPTUFQM19DT1JFMV9JT1BBRCgw eDIwZGMsIFBJTl9PVVRQVVQgfCBNVVhfTU9ERTEpIC8qIGRzaV9keDAgLQo+IGRhdGEwKyAqLwo+ ICsJCQlPTUFQM19DT1JFMV9JT1BBRCgweDIwZGUsIFBJTl9PVVRQVVQgfCBNVVhfTU9ERTEpIC8q IGRzaV9keTAgLQo+IGRhdGEwLSAqLwo+ICsJCQlPTUFQM19DT1JFMV9JT1BBRCgweDIwZTAsIFBJ Tl9PVVRQVVQgfCBNVVhfTU9ERTEpIC8qIGRzaV9keDEgLQo+IGNsaysgICAqLwo+ICsJCQlPTUFQ M19DT1JFMV9JT1BBRCgweDIwZTIsIFBJTl9PVVRQVVQgfCBNVVhfTU9ERTEpIC8qIGRzaV9keTEg LQo+IGNsay0gICAqLwo+ICsJCQlPTUFQM19DT1JFMV9JT1BBRCgweDIwZTQsIFBJTl9PVVRQVVQg fCBNVVhfTU9ERTEpIC8qIGRzaV9keDIgLQo+IGRhdGExKyAqLwo+ICsJCQlPTUFQM19DT1JFMV9J T1BBRCgweDIwZTYsIFBJTl9PVVRQVVQgfCBNVVhfTU9ERTEpIC8qIGRzaV9keTIgLQo+IGRhdGEx LSAqLwo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCWRpc3BsYXlfcGluczogcGlubXV4X2Rpc3BsYXlf cGlucyB7Cj4gKwkJcGluY3RybC1zaW5nbGUscGlucyA9IDwKPiArCQkJT01BUDNfQ09SRTFfSU9Q QUQoMHgyMGNhLCBQSU5fSU5QVVQgfCBNVVhfTU9ERTQpIC8qIGdwaW8gNjIgLQo+IGRpc3BsYXkg dGUgKi8KPiArCQkJT01BUDNfQ09SRTFfSU9QQUQoMHgyMGZlLCBQSU5fT1VUUFVUIHwgTVVYX01P REU0KSAvKiBncGlvIDg3IC0KPiBkaXNwbGF5IHJlc2V0ICovCj4gKwkJPjsKPiArCX07Cj4gK307 Cj4gKwo+ICAmaTJjMiB7Cj4gIAlzbWlhXzE6IGNhbWVyYUAxMCB7Cj4gIAkJY29tcGF0aWJsZSA9 ICJub2tpYSxzbWlhIjsKPiBAQCAtNTMsMyArNzMsNTQgQEAKPiAgCQl9Owo+ICAJfTsKPiAgfTsK PiArCj4gKyZkc3Mgewo+ICsJc3RhdHVzID0gIm9rIjsKPiArCj4gKwl2ZGRhX3ZpZGVvLXN1cHBs eSA9IDwmdmRhYz47Cj4gK307Cj4gKwo+ICsmZHNpIHsKPiArCXN0YXR1cyA9ICJvayI7Cj4gKwo+ ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsKPiArCXBpbmN0cmwtMCA9IDwmZHNpX3BpbnM+ Owo+ICsKPiArCXZkZC1zdXBwbHkgPSA8JnZwbGwyPjsKPiArCj4gKwlwb3J0IHsKPiArCQlkc2lf b3V0X2VwOiBlbmRwb2ludCB7Cj4gKwkJCXJlbW90ZS1lbmRwb2ludCA9IDwmbGNkMF9pbj47Cj4g KwkJCWxhbmVzID0gPDIgMyAwIDEgNCA1PjsKPiArCQl9Owo+ICsJfTsKPiArCj4gKwlsY2QwOiBk aXNwbGF5IHsKPiArCQljb21wYXRpYmxlID0gIm5va2lhLGhpbWFsYXlhIiwgInBhbmVsLWRzaS1j bSI7Cj4gKwkJbGFiZWwgPSAibGNkMCI7Cj4gKwo+ICsJCXBpbmN0cmwtbmFtZXMgPSAiZGVmYXVs dCI7Cj4gKwkJcGluY3RybC0wID0gPCZkaXNwbGF5X3BpbnM+Owo+ICsKPiArCQl2cG5sLXN1cHBs eSA9IDwmdm1tYzI+Owo+ICsJCXZkZGktc3VwcGx5ID0gPCZ2aW8+Owo+ICsKPiArCQlyZXNldC1n cGlvcyA9IDwmZ3BpbzMgMjMgR1BJT19BQ1RJVkVfSElHSD47CS8qIDg3ICovCj4gKwkJdGUtZ3Bp b3MgPSA8JmdwaW8yIDMwIEdQSU9fQUNUSVZFX0hJR0g+OwkvKiA2MiAqLwo+ICsKPiArCQloYXMt ZHNpLWJhY2tsaWdodDsKPiArCj4gKwkJLyogcGFuZWwgaXMgNDgweDQ2NCB3aXRoIHRvcCBhbmQg Ym90dG9tIDUgbGluZXMgbm90IHZpc2libGUgKi8KCkkgYXNzdW1lIHlvdSBtZWFuIDQ4MHg4NjQg PwoKPiArCQkvKiBwaHlzaWNhbCBkaW1lbnNpb25zOiA0ODk2MMK1bSB4IDg4MTI4wrVtICovCj4g KwkJcmVzb2x1dGlvbi14ID0gPDQ4MD47Cj4gKwkJcmVzb2x1dGlvbi15ID0gPDg1ND47Cj4gKwkJ b2Zmc2V0LXggPSA8MD47Cj4gKwkJb2Zmc2V0LXkgPSA8NT47Cj4gKwo+ICsJCXBvcnQgewo+ICsJ CQlsY2QwX2luOiBlbmRwb2ludCB7Cj4gKwkJCQlyZW1vdGUtZW5kcG9pbnQgPSA8JmRzaV9vdXRf ZXA+Owo+ICsJCQl9Owo+ICsJCX07Cj4gKwl9Owo+ICt9OwoKLS0gClJlZ2FyZHMsCgpMYXVyZW50 IFBpbmNoYXJ0CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f XwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcK aHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK