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References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de>
	<20181020071451.27808-17-kbastian@mail.uni-paderborn.de>
From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <2180857a-281a-0298-7486-9067f8ed5905@linaro.org>
Date: Tue, 23 Oct 2018 09:31:23 +0100
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Subject: Re: [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0
 of RVXC insns to decodetree
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To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com
Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org

On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> v1 -> v2:
>     - Stack allocate arg_c_* structs
>     - ex_rvc_register returns int
>     - special case of trans_c_addi4spn() returns false
...
> +static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a,
> +        uint16_t insn)
> +{
> +    if (a->nzuimm == 0) {
> +        /* Reserved in ISA */
> +        gen_exception_illegal(ctx);
> +        return true;
> +    }

That doesn't seem to have actually happened.

But otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~