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From: Jan Beulich <jbeulich@suse.com>
To: David Woodhouse <dwmw2@infradead.org>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Wei Liu" <wl@xen.org>,
	xen-devel@lists.xenproject.org,
	"Roger Pau Monné" <roger.pau@citrix.com>
Subject: Re: [PATCH 1/3] xen/vioapic: add support for the extended destination ID field
Date: Wed, 26 Jan 2022 15:23:42 +0100	[thread overview]
Message-ID: <21e443f7-ce72-af39-587f-6e40e72625a9@suse.com> (raw)
In-Reply-To: <a984ffd4bbadb1cf550e7a980f81db250b3b69c1.camel@infradead.org>

On 26.01.2022 14:52, David Woodhouse wrote:
> On Tue, 2022-01-25 at 16:13 +0100, Roger Pau Monné wrote:
>> On Mon, Jan 24, 2022 at 02:20:47PM +0100, Jan Beulich wrote:
>>> On 20.01.2022 16:23, Roger Pau Monne wrote:
>>>> Such field uses bits 55:48, but for the purposes the register will be
>>>> used use bits 55:49 instead. Bit 48 is used to signal an RTE entry is
>>>> in remappable format which is not supported by the vIO-APIC.
>>>
>>> Neither here nor in the cover letter you point at a formal specification
>>> of this mode of operation.
>>
>> I'm not aware of any formal specification of this mode, apart from the
>> work done to introduce support in Linux and QEMU:
>>
>> https://lore.kernel.org/all/20201009104616.1314746-1-dwmw2@infradead.org/
>>
>> https://git.qemu.org/?p=qemu.git;a=commitdiff;h=c1bb5418e
>>
>>
>> Adding David in case there's some kind of specification somewhere I'm
>> not aware of.
> 
> Indeed there is no formal specification that I am aware of, although
> it's vaguely possible that Microsoft wrote something up when they added
> it to Hyper-V.
> 
> https://lore.kernel.org/all/20201103011136.59108-1-decui@microsoft.com/
> 
> I had an internal doc which.... looks like I can clean it up a tiny bit
> and then share at http://david.woodhou.se/15-bit-msi.pdf if that helps?

Thanks, this at least puts us on common grounds.

>>> What I'm aware of are vague indications of
>>> this mode's existence in some of Intel's chipset data sheets. Yet that
>>> leaves open, for example, whether indeed bit 48 cannot be used here.
>>
>> Bit 48 cannot be used because it's already used to signal an RTE is in
>> remappable format. We still want to differentiate an RTE entry in
>> remappable format, as it should be possible to expose both the
>> extended ID support and an emulated IOMMU.
> 
> Right. I chose not to use the low bit of the existing Extended
> Destination ID because that's the one Intel used to indicate Remappable
> Format. This means we can still expose an IOMMU to guests and easily
> distinguish between Compatibility Format and Remappable Format MSIs
> just as real hardware does.

Well, with the defacto standard of using only 7 of the bits we will
have to follow suit of course.

Jan



  reply	other threads:[~2022-01-26 14:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-20 15:23 [PATCH 0/3] x86/hvm: add support for extended destination ID Roger Pau Monne
2022-01-20 15:23 ` [PATCH 1/3] xen/vioapic: add support for the extended destination ID field Roger Pau Monne
2022-01-24 13:20   ` Jan Beulich
2022-01-25 15:13     ` Roger Pau Monné
2022-01-26 12:47       ` Jan Beulich
2022-01-26 19:21         ` David Woodhouse
2022-01-26 13:52       ` David Woodhouse
2022-01-26 14:23         ` Jan Beulich [this message]
2022-01-20 15:23 ` [PATCH 2/3] x86/vmsi: add support for extended destination ID in address field Roger Pau Monne
2022-01-24 13:47   ` Jan Beulich
2022-01-26 13:54     ` David Woodhouse
2022-01-26 14:22       ` Roger Pau Monné
2022-02-04  9:23     ` Roger Pau Monné
2022-02-04  9:30       ` Jan Beulich
2022-02-04  9:54         ` Roger Pau Monné
2022-02-04 10:20           ` Jan Beulich
2022-01-20 15:23 ` [PATCH 3/3] HACK: allow adding an offset to the x2APIC ID Roger Pau Monne
2022-01-26 14:03   ` David Woodhouse

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