From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=FROM_EXCESS_BASE64, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E052CC7618B for ; Mon, 29 Jul 2019 15:55:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF2BA206B8 for ; Mon, 29 Jul 2019 15:55:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388227AbfG2Pz4 convert rfc822-to-8bit (ORCPT ); Mon, 29 Jul 2019 11:55:56 -0400 Received: from mailoutvs54.siol.net ([185.57.226.245]:56000 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2387593AbfG2Pz4 (ORCPT ); Mon, 29 Jul 2019 11:55:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTP id 8DCAD522BB3; Mon, 29 Jul 2019 17:55:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at psrvmta12.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta12.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id u-_fD2Ny9KTo; Mon, 29 Jul 2019 17:55:53 +0200 (CEST) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTPS id 266D5522D23; Mon, 29 Jul 2019 17:55:53 +0200 (CEST) Received: from jernej-laptop.localnet (cpe-194-152-11-237.cable.triera.net [194.152.11.237]) (Authenticated sender: jernej.skrabec@siol.net) by mail.siol.net (Zimbra) with ESMTPA id A1875522BB3; Mon, 29 Jul 2019 17:55:52 +0200 (CEST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Uwe =?ISO-8859-1?Q?Kleine=2DK=F6nig?= Cc: thierry.reding@gmail.com, mripard@kernel.org, wens@csie.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, kernel@pengutronix.de Subject: Re: [PATCH 4/6] pwm: sun4i: Add support for H6 PWM Date: Mon, 29 Jul 2019 17:55:52 +0200 Message-ID: <223488703.0I5IR7NXoI@jernej-laptop> In-Reply-To: <20190729064030.7uenld2kbof45zti@pengutronix.de> References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-5-jernej.skrabec@siol.net> <20190729064030.7uenld2kbof45zti@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Uwe, Dne ponedeljek, 29. julij 2019 ob 08:40:30 CEST je Uwe Kleine-König napisal(a): > On Fri, Jul 26, 2019 at 08:40:43PM +0200, Jernej Skrabec wrote: > > Now that sun4i PWM driver supports deasserting reset line and enabling > > bus clock, support for H6 PWM can be added. > > > > Note that while H6 PWM has two channels, only first one is wired to > > output pin. Second channel is used as a clock source to companion AC200 > > chip which is bundled into same package. > > > > Signed-off-by: Jernej Skrabec > > --- > > > > drivers/pwm/pwm-sun4i.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 7d3ac3f2dc3f..9e0eca79ff88 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -331,6 +331,13 @@ static const struct sun4i_pwm_data > > sun4i_pwm_single_bypass = {> > > .npwm = 1, > > > > }; > > > > +static const struct sun4i_pwm_data sun50i_pwm_dual_bypass_clk_rst = { > > + .has_bus_clock = true, > > + .has_prescaler_bypass = true, > > + .has_reset = true, > > + .npwm = 2, > > +}; > > + > > > > static const struct of_device_id sun4i_pwm_dt_ids[] = { > > > > { > > > > .compatible = "allwinner,sun4i-a10-pwm", > > > > @@ -347,6 +354,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = > > { > > > > }, { > > > > .compatible = "allwinner,sun8i-h3-pwm", > > .data = &sun4i_pwm_single_bypass, > > > > + }, { > > + .compatible = "allwinner,sun50i-h6-pwm", > > + .data = &sun50i_pwm_dual_bypass_clk_rst, > > If you follow my suggestion for the two previous patches, you can just > use: > > compatible = "allwinner,sun50i-h6-pwm", "allwinner,sun5i-a10s-pwm"; > > and drop this patch. Maxime found out that it's not compatible with A10s due to difference in bypass bit, but yes, I know what you mean. Since H6 requires reset line and bus clock to be specified, it's not compatible from DT binding side. New yaml based binding must somehow know that in order to be able to validate DT node, so it needs standalone compatible. However, depending on conclusions of other discussions, this new compatible can be associated with already available quirks structure or have it's own. Best regards, Jernej > > Best regards > Uwe > > > }, { > > > > /* sentinel */ > > > > }, From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jernej =?utf-8?B?xaBrcmFiZWM=?= Subject: Re: [PATCH 4/6] pwm: sun4i: Add support for H6 PWM Date: Mon, 29 Jul 2019 17:55:52 +0200 Message-ID: <223488703.0I5IR7NXoI@jernej-laptop> References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-5-jernej.skrabec@siol.net> <20190729064030.7uenld2kbof45zti@pengutronix.de> Reply-To: jernej.skrabec-gGgVlfcn5nU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20190729064030.7uenld2kbof45zti-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Uwe =?ISO-8859-1?Q?Kleine=2DK=F6nig?= Cc: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, mripard-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org List-Id: devicetree@vger.kernel.org Hi Uwe, Dne ponedeljek, 29. julij 2019 ob 08:40:30 CEST je Uwe Kleine-K=C3=B6nig=20 napisal(a): > On Fri, Jul 26, 2019 at 08:40:43PM +0200, Jernej Skrabec wrote: > > Now that sun4i PWM driver supports deasserting reset line and enabling > > bus clock, support for H6 PWM can be added. > >=20 > > Note that while H6 PWM has two channels, only first one is wired to > > output pin. Second channel is used as a clock source to companion AC200 > > chip which is bundled into same package. > >=20 > > Signed-off-by: Jernej Skrabec > > --- > >=20 > > drivers/pwm/pwm-sun4i.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > >=20 > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 7d3ac3f2dc3f..9e0eca79ff88 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -331,6 +331,13 @@ static const struct sun4i_pwm_data > > sun4i_pwm_single_bypass =3D {>=20 > > .npwm =3D 1, > > =20 > > }; > >=20 > > +static const struct sun4i_pwm_data sun50i_pwm_dual_bypass_clk_rst =3D = { > > + .has_bus_clock =3D true, > > + .has_prescaler_bypass =3D true, > > + .has_reset =3D true, > > + .npwm =3D 2, > > +}; > > + > >=20 > > static const struct of_device_id sun4i_pwm_dt_ids[] =3D { > > =20 > > { > > =09 > > .compatible =3D "allwinner,sun4i-a10-pwm", > >=20 > > @@ -347,6 +354,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[]= =3D > > { > >=20 > > }, { > > =09 > > .compatible =3D "allwinner,sun8i-h3-pwm", > > .data =3D &sun4i_pwm_single_bypass, > >=20 > > + }, { > > + .compatible =3D "allwinner,sun50i-h6-pwm", > > + .data =3D &sun50i_pwm_dual_bypass_clk_rst, >=20 > If you follow my suggestion for the two previous patches, you can just > use: >=20 > compatible =3D "allwinner,sun50i-h6-pwm", "allwinner,sun5i-a10s-pwm"; >=20 > and drop this patch. Maxime found out that it's not compatible with A10s due to difference in by= pass=20 bit, but yes, I know what you mean. Since H6 requires reset line and bus clock to be specified, it's not compat= ible=20 from DT binding side. New yaml based binding must somehow know that in orde= r=20 to be able to validate DT node, so it needs standalone compatible. However,= =20 depending on conclusions of other discussions, this new compatible can be= =20 associated with already available quirks structure or have it's own. Best regards, Jernej >=20 > Best regards > Uwe >=20 > > }, { > > =09 > > /* sentinel */ > > =09 > > }, --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org To view this discussion on the web, visit https://groups.google.com/d/msgid= /linux-sunxi/223488703.0I5IR7NXoI%40jernej-laptop. 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Mon, 29 Jul 2019 17:55:52 +0200 (CEST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Uwe =?ISO-8859-1?Q?Kleine=2DK=F6nig?= Subject: Re: [PATCH 4/6] pwm: sun4i: Add support for H6 PWM Date: Mon, 29 Jul 2019 17:55:52 +0200 Message-ID: <223488703.0I5IR7NXoI@jernej-laptop> In-Reply-To: <20190729064030.7uenld2kbof45zti@pengutronix.de> References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-5-jernej.skrabec@siol.net> <20190729064030.7uenld2kbof45zti@pengutronix.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190729_085556_711511_190D280D X-CRM114-Status: GOOD ( 17.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, mripard@kernel.org, wens@csie.org, robh+dt@kernel.org, thierry.reding@gmail.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Uwe, Dne ponedeljek, 29. julij 2019 ob 08:40:30 CEST je Uwe Kleine-K=F6nig = napisal(a): > On Fri, Jul 26, 2019 at 08:40:43PM +0200, Jernej Skrabec wrote: > > Now that sun4i PWM driver supports deasserting reset line and enabling > > bus clock, support for H6 PWM can be added. > > = > > Note that while H6 PWM has two channels, only first one is wired to > > output pin. Second channel is used as a clock source to companion AC200 > > chip which is bundled into same package. > > = > > Signed-off-by: Jernej Skrabec > > --- > > = > > drivers/pwm/pwm-sun4i.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > = > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 7d3ac3f2dc3f..9e0eca79ff88 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -331,6 +331,13 @@ static const struct sun4i_pwm_data > > sun4i_pwm_single_bypass =3D {> = > > .npwm =3D 1, > > = > > }; > > = > > +static const struct sun4i_pwm_data sun50i_pwm_dual_bypass_clk_rst =3D { > > + .has_bus_clock =3D true, > > + .has_prescaler_bypass =3D true, > > + .has_reset =3D true, > > + .npwm =3D 2, > > +}; > > + > > = > > static const struct of_device_id sun4i_pwm_dt_ids[] =3D { > > = > > { > > = > > .compatible =3D "allwinner,sun4i-a10-pwm", > > = > > @@ -347,6 +354,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[]= =3D > > { > > = > > }, { > > = > > .compatible =3D "allwinner,sun8i-h3-pwm", > > .data =3D &sun4i_pwm_single_bypass, > > = > > + }, { > > + .compatible =3D "allwinner,sun50i-h6-pwm", > > + .data =3D &sun50i_pwm_dual_bypass_clk_rst, > = > If you follow my suggestion for the two previous patches, you can just > use: > = > compatible =3D "allwinner,sun50i-h6-pwm", "allwinner,sun5i-a10s-pwm"; > = > and drop this patch. Maxime found out that it's not compatible with A10s due to difference in by= pass = bit, but yes, I know what you mean. Since H6 requires reset line and bus clock to be specified, it's not compat= ible = from DT binding side. New yaml based binding must somehow know that in orde= r = to be able to validate DT node, so it needs standalone compatible. However, = depending on conclusions of other discussions, this new compatible can be = associated with already available quirks structure or have it's own. Best regards, Jernej > = > Best regards > Uwe > = > > }, { > > = > > /* sentinel */ > > = > > }, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel