From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934194AbcAZMM0 (ORCPT ); Tue, 26 Jan 2016 07:12:26 -0500 Received: from mout.kundenserver.de ([217.72.192.73]:60008 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755892AbcAZMMV (ORCPT ); Tue, 26 Jan 2016 07:12:21 -0500 From: Arnd Bergmann To: Michal Simek Cc: Bharat Kumar Gogada , bhelgaas@google.com, lorenzo.pieralisi@arm.com, paul.burton@imgtec.com, yinghai@kernel.org, wangyijing@huawei.com, robh@kernel.org, russell.joyce@york.ac.uk, sorenb@xilinx.com, jiang.liu@linux.intel.com, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Bharat Kumar Gogada , Ravi Kiran Gummaluri Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Tue, 26 Jan 2016 13:11:20 +0100 Message-ID: <2270955.TlqP7HlQk4@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <56A74370.4090000@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> <56A74370.4090000@xilinx.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:JdaoZFiSwKL0RpKTwpKW/q7le0xlvop+xlWH836VhNKCkIWHMjV WQpD3hIh2MHXRSlErsJv7oXXJ9UjFFw/UsX5BZv1iFyKGabUHG9hQlLjALhmNU7HOmFI0Fb H+pKOrUPjWqc5T6K3JBzN9EFR8dkMnVFK1ZNMkhRVNKbL4yf08sKPSQbp2DTaMJl0fqtQ3G bO80U3crINDvkh4qbgE4g== X-UI-Out-Filterresults: notjunk:1;V01:K0:Qu5euzWPK5M=:hCa9YKlhzc3k915vGS1+/s UAIlTujVMa8aSCbZnJbDY09wRFqZ3nk8stBPGcyK6hNqPosxRH0xqamyvmzcNodtSv4YYLgTT 4BAYx/q8HXUBRj870TAI/JBBOgd5Hc+RQH4FWHhh7GTXhBg+sE4Ow57HIW1fYZMSbkYqsUQbB EBCP8inAa7/9cNoZgO/yt96Fy+B/pszC714dGEAO0W5QQ8jQG3uu0Ed3O5dFTsyU4y4UyVy7q GPu+CgymsBxDZ/o5uZppK7xQl/tqjspgR2I963TFoqGrqDLvxbiab6RDx0+GqcxGjZwl7/F4U qOAKjz1YdkJaNFWVxlloSITa7h/ToS/F5oI9POaNXkIGJ9mYVE/jTjlMmTY5/mrV6Cb4dfr+/ eYeX2Rh/Sj9oQ/wAtJfcOZRCpMDNFr6/XNaHOaVlgX96vfxiG0w9xCGAz0fUJPXY/u13vE8OP F8irf8G90DhAx+Af/YyhdFSy/1F5NaTjq9+l+/5/XZI2dBag1yWUy21HUDxZ+SRQSWx3EycFE AaaDIvgB50iTzd6bo6PYgMIY9ey2xq24TPfby9LZhGr+9jz7Fo/13zaPvjVbpojL1PN/gXOQ6 oHL/c/hOc4GtT+aIXuRfEtX7j3DQa6SluUMVLdOTWGYPquADQ137lQ08mixsqjOjx4Q24iK6s By+LeN04m3RP9IZMgS/V+uW6sDauiEedjCo9waEt5Ybu2THhIGIT7nNY8WelTh2PzurgppG61 TYPiULsuoyTGmYef Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 26 January 2016 10:59:12 Michal Simek wrote: > >> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c > >> index 3e3757f..1981948 100644 > >> --- a/drivers/pci/host/pcie-xilinx.c > >> +++ b/drivers/pci/host/pcie-xilinx.c > >> @@ -92,7 +92,12 @@ > >> #define ECAM_DEV_NUM_SHIFT 12 > >> > >> /* Number of MSI IRQs */ > >> -#define XILINX_NUM_MSI_IRQS 128 > >> +#define XILINX_NUM_MSI_IRQS 128 > >> +#ifdef CONFIG_ARM > >> +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS > >> +#else > >> +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) > >> +#endif > > > > Something looks wrong here in the microblaze variant. What does NR_IRQS > > have to do with it? > > Arnd: What was the story regarding NR_IRQS? > I remember some discussion about it but just forget. > > Default value in include/asm-generic/irq.h is 64. > Current value is 32 because microblaze primary interrupt controller is > axi_intc core which has up to 32 input lines. The value in asm-generic is completely arbitrary, it's just something that happens to work for a number of the simpler architectures. Traditionally, there is a a fixed NR_IRQS which defines the maximum number of interrupts that can be used, and each irqchip has a fixed start offset below that number. On modern systems, you have CONFIG_SPARSE_IRQ, which lets an irqchip allocate its own interrupts, without an upper limit. This is more flexible and avoids preallocating space for all irq_desc instances, so it saves memory. This code however doesn't do either of the two on microblaze: + irq = pos; +#ifdef CONFIG_MICROBLAZE +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) + irq = XILINX_NUM_MSI_IRQS + pos; +#endif + if (irq < TOT_NR_IRQS) set_bit(pos, msi_irq_in_use); So you define XILINX_NUM_MSI_IRQS to mean the number of interrupts that the xilinx_pcie_port can handle itself, but then pick a number outside of this range by making the hwirq number something between XILINX_NUM_MSI_IRQS and (2*XILINX_NUM_MSI_IRQS - 1), and in the end compare it to (NR_IRQS + XILINX_NUM_MSI_IRQS), which is the sum of two things that are not related: the total number of interrupts including the MSIs and the number of MSI. Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Tue, 26 Jan 2016 13:11:20 +0100 Message-ID: <2270955.TlqP7HlQk4@wuerfel> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> <56A74370.4090000@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <56A74370.4090000@xilinx.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Michal Simek Cc: mark.rutland@arm.com, lorenzo.pieralisi@arm.com, pawel.moll@arm.com, paul.burton@imgtec.com, ijc+devicetree@hellion.org.uk, Bharat Kumar Gogada , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, russell.joyce@york.ac.uk, Bharat Kumar Gogada , wangyijing@huawei.com, devicetree@vger.kernel.org, Ravi Kiran Gummaluri , sorenb@xilinx.com, galak@codeaurora.org, bhelgaas@google.com, yinghai@kernel.org, jiang.liu@linux.intel.com, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org On Tuesday 26 January 2016 10:59:12 Michal Simek wrote: > >> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c > >> index 3e3757f..1981948 100644 > >> --- a/drivers/pci/host/pcie-xilinx.c > >> +++ b/drivers/pci/host/pcie-xilinx.c > >> @@ -92,7 +92,12 @@ > >> #define ECAM_DEV_NUM_SHIFT 12 > >> > >> /* Number of MSI IRQs */ > >> -#define XILINX_NUM_MSI_IRQS 128 > >> +#define XILINX_NUM_MSI_IRQS 128 > >> +#ifdef CONFIG_ARM > >> +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS > >> +#else > >> +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) > >> +#endif > > > > Something looks wrong here in the microblaze variant. What does NR_IRQS > > have to do with it? > > Arnd: What was the story regarding NR_IRQS? > I remember some discussion about it but just forget. > > Default value in include/asm-generic/irq.h is 64. > Current value is 32 because microblaze primary interrupt controller is > axi_intc core which has up to 32 input lines. The value in asm-generic is completely arbitrary, it's just something that happens to work for a number of the simpler architectures. Traditionally, there is a a fixed NR_IRQS which defines the maximum number of interrupts that can be used, and each irqchip has a fixed start offset below that number. On modern systems, you have CONFIG_SPARSE_IRQ, which lets an irqchip allocate its own interrupts, without an upper limit. This is more flexible and avoids preallocating space for all irq_desc instances, so it saves memory. This code however doesn't do either of the two on microblaze: + irq = pos; +#ifdef CONFIG_MICROBLAZE +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) + irq = XILINX_NUM_MSI_IRQS + pos; +#endif + if (irq < TOT_NR_IRQS) set_bit(pos, msi_irq_in_use); So you define XILINX_NUM_MSI_IRQS to mean the number of interrupts that the xilinx_pcie_port can handle itself, but then pick a number outside of this range by making the hwirq number something between XILINX_NUM_MSI_IRQS and (2*XILINX_NUM_MSI_IRQS - 1), and in the end compare it to (NR_IRQS + XILINX_NUM_MSI_IRQS), which is the sum of two things that are not related: the total number of interrupts including the MSIs and the number of MSI. Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: arnd@arndb.de (Arnd Bergmann) Date: Tue, 26 Jan 2016 13:11:20 +0100 Subject: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze In-Reply-To: <56A74370.4090000@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> <56A74370.4090000@xilinx.com> Message-ID: <2270955.TlqP7HlQk4@wuerfel> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tuesday 26 January 2016 10:59:12 Michal Simek wrote: > >> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c > >> index 3e3757f..1981948 100644 > >> --- a/drivers/pci/host/pcie-xilinx.c > >> +++ b/drivers/pci/host/pcie-xilinx.c > >> @@ -92,7 +92,12 @@ > >> #define ECAM_DEV_NUM_SHIFT 12 > >> > >> /* Number of MSI IRQs */ > >> -#define XILINX_NUM_MSI_IRQS 128 > >> +#define XILINX_NUM_MSI_IRQS 128 > >> +#ifdef CONFIG_ARM > >> +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS > >> +#else > >> +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) > >> +#endif > > > > Something looks wrong here in the microblaze variant. What does NR_IRQS > > have to do with it? > > Arnd: What was the story regarding NR_IRQS? > I remember some discussion about it but just forget. > > Default value in include/asm-generic/irq.h is 64. > Current value is 32 because microblaze primary interrupt controller is > axi_intc core which has up to 32 input lines. The value in asm-generic is completely arbitrary, it's just something that happens to work for a number of the simpler architectures. Traditionally, there is a a fixed NR_IRQS which defines the maximum number of interrupts that can be used, and each irqchip has a fixed start offset below that number. On modern systems, you have CONFIG_SPARSE_IRQ, which lets an irqchip allocate its own interrupts, without an upper limit. This is more flexible and avoids preallocating space for all irq_desc instances, so it saves memory. This code however doesn't do either of the two on microblaze: + irq = pos; +#ifdef CONFIG_MICROBLAZE +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) + irq = XILINX_NUM_MSI_IRQS + pos; +#endif + if (irq < TOT_NR_IRQS) set_bit(pos, msi_irq_in_use); So you define XILINX_NUM_MSI_IRQS to mean the number of interrupts that the xilinx_pcie_port can handle itself, but then pick a number outside of this range by making the hwirq number something between XILINX_NUM_MSI_IRQS and (2*XILINX_NUM_MSI_IRQS - 1), and in the end compare it to (NR_IRQS + XILINX_NUM_MSI_IRQS), which is the sum of two things that are not related: the total number of interrupts including the MSIs and the number of MSI. Arnd