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([2a02:908:1252:fb60:4405:6e4f:ef81:78d1]) by smtp.gmail.com with ESMTPSA id q7sm1665482wrc.55.2021.09.29.02.23.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Sep 2021 02:23:09 -0700 (PDT) Subject: Re: [PATCH 61/64] drm/amdgpu: add support for SRIOV in IP discovery path To: Alex Deucher , amd-gfx@lists.freedesktop.org References: <20210928164237.833132-1-alexander.deucher@amd.com> <20210928164237.833132-62-alexander.deucher@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: <22b1a4c6-cd0b-4700-3cb3-b0b9f3528982@gmail.com> Date: Wed, 29 Sep 2021 11:23:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210928164237.833132-62-alexander.deucher@amd.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 28.09.21 um 18:42 schrieb Alex Deucher: > Handle SRIOV requirements when adding IP blocks. > > v2: add comment about UVD/VCE support on vega20 SR-IOV > > Signed-off-by: Alex Deucher Acked-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 34 ++++++++++++++----- > 1 file changed, 25 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > index d9c2a7210a1b..091ded38545f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > @@ -820,7 +820,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) > switch (adev->ip_versions[UVD_HWIP][0]) { > case IP_VERSION(7, 0, 0): > case IP_VERSION(7, 2, 0): > - amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); > + /* UVD is not supported on vega20 SR-IOV */ > + if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) > + amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); > break; > default: > return -EINVAL; > @@ -828,7 +830,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) > switch (adev->ip_versions[VCE_HWIP][0]) { > case IP_VERSION(4, 0, 0): > case IP_VERSION(4, 1, 0): > - amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); > + /* VCE is not supported on vega20 SR-IOV */ > + if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) > + amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); > break; > default: > return -EINVAL; > @@ -860,7 +864,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) > case IP_VERSION(3, 1, 1): > case IP_VERSION(3, 0, 2): > amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); > - amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); > + if (!amdgpu_sriov_vf(adev)) > + amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); > break; > case IP_VERSION(3, 0, 33): > amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); > @@ -1202,14 +1207,24 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) > if (r) > return r; > > - r = amdgpu_discovery_set_ih_ip_blocks(adev); > - if (r) > - return r; > - > - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { > + /* For SR-IOV, PSP needs to be initialized before IH */ > + if (amdgpu_sriov_vf(adev)) { > r = amdgpu_discovery_set_psp_ip_blocks(adev); > if (r) > return r; > + r = amdgpu_discovery_set_ih_ip_blocks(adev); > + if (r) > + return r; > + } else { > + r = amdgpu_discovery_set_ih_ip_blocks(adev); > + if (r) > + return r; > + > + if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { > + r = amdgpu_discovery_set_psp_ip_blocks(adev); > + if (r) > + return r; > + } > } > > if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { > @@ -1230,7 +1245,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) > if (r) > return r; > > - if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { > + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && > + !amdgpu_sriov_vf(adev)) { > r = amdgpu_discovery_set_smu_ip_blocks(adev); > if (r) > return r;