From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755935AbcLNN2Q (ORCPT ); Wed, 14 Dec 2016 08:28:16 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:60976 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755436AbcLNN2N (ORCPT ); Wed, 14 Dec 2016 08:28:13 -0500 X-AuditID: cbfee61a-f79916d0000062de-cd-585148e83106 From: Bartlomiej Zolnierkiewicz To: Javier Martinez Canillas , Arjun K V Cc: Krzysztof Kozlowski , Kukjin Kim , Rob Herring , Mark Rutland , Russell King , Doug Anderson , Andreas Faerber , Thomas Abraham , Ben Gamari , linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: dts: Add missing CPU frequencies for Exynos5422/5800 Date: Wed, 14 Dec 2016 14:28:06 +0100 Message-id: <2340115.HEG9AYUCMD@amdc3058> User-Agent: KMail/4.13.3 (Linux/3.13.0-96-generic; KDE/4.13.3; x86_64; ; ) In-reply-to: <26ffeee4-ff43-b3d3-3267-5fcbc50e2974@osg.samsung.com> References: <5220084.l31t5oJbsy@amdc3058> <26ffeee4-ff43-b3d3-3267-5fcbc50e2974@osg.samsung.com> MIME-version: 1.0 Content-transfer-encoding: 7Bit Content-type: text/plain; charset=us-ascii X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBIsWRmVeSWpSXmKPExsVy+t9jAd0XHoERBpNua1s0byq2WL5yF4vF rPl3WSzmHznHanF22UE2izdv1zBZ9D9+zWxx/vwGdotNj6+xWlzeNYfN4nPvEUaLGef3MVkc mrqX0WLp9YtMFq17j7BbdCxjdBDwWDNvDaPH5WsXmT1mN1xk8di0qpPNY/OSeo8t/XfZPfq2 rGL0OPPb2WPz6WqPz5vkArii3GwyUhNTUosUUvOS81My89JtlUJD3HQtlBTyEnNTbZUidH1D gpQUyhJzSoE8IwM04OAc4B6spG+X4JaxbvFBloL1JhV3XmxjbGCco9nFyMkhIWAicWDqK2YI W0ziwr31bF2MXBxCAksZJXbsbGGFcL4ySuxq/sMKUsUmYCUxsX0VI4gtIhApsXHWESaQImaB L8wSvz9eBUsIC/hJPDv+FqyBRUBV4vPFV+wgNq+ApsSWiwfAakQFvCS27GtnArE5BZwlNs5c zgKxbRujxO6vyxghGgQlfky+xwJiMwvIS+zbP5UVwtaSWL/zONMERoFZSMpmISmbhaRsASPz KkaJ1ILkguKk9FzDvNRyveLE3OLSvHS95PzcTYzgWH8mtYPx4C73Q4wCHIxKPLwLBAMihFgT y4orcw8xSnAwK4nwGrsERgjxpiRWVqUW5ccXleakFh9iNAX6cCKzlGhyPjAN5ZXEG5qYm5gb G1iYW1qaGCmJ8zbOfhYuJJCeWJKanZpakFoE08fEwSnVwJj4cKGnyGQJoaVHDzHfevqX86rc Xi+7L3nRMf0PFgTf4pop6nk3nalSzfRBgeQnl4zmY3ckddP/OScKLuQTbZZ5JXF1D/vy033n /m0wY2v2/arj2XtfcsHsTospLj/DD9qJ7NHRXB2hpSwZwPynqVZ5/u3GBT7nDMQ6j+xc6yio spbbNKDklRJLcUaioRZzUXEiAApTzIELAwAA X-MTR: 20000000000000000@CPGS Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday, December 13, 2016 04:18:05 PM Javier Martinez Canillas wrote: > Hello Bartlomiej, Hi, > On 12/13/2016 01:52 PM, Bartlomiej Zolnierkiewicz wrote: > > Add missing 2000MHz & 1900MHz OPPs (for A15 cores) and 1400MHz OPP > > (for A7 cores). Also update common Odroid-XU3 Lite/XU3/XU4 thermal > > cooling maps to account for new OPPs. > > > > Since new OPPs are not available on all Exynos5422/5800 boards modify > > dts files for Odroid-XU3 Lite (limited to 1.8 GHz / 1.3 GHz) & Peach > > Pi (limited to 2.0 GHz / 1.3 GHz) accordingly. > > > > Tested on Odroid-XU3 and XU3 Lite. > > > > Cc: Doug Anderson > > Cc: Javier Martinez Canillas > > Cc: Andreas Faerber > > Cc: Thomas Abraham > > Cc: Ben Gamari > > Signed-off-by: Bartlomiej Zolnierkiewicz > > --- > > arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 14 +++++++------- > > arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 17 +++++++++++++++++ > > arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++++ > > arch/arm/boot/dts/exynos5800.dtsi | 15 +++++++++++++++ > > 4 files changed, 43 insertions(+), 7 deletions(-) > > > > Index: b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi > > =================================================================== > > --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 2016-12-13 15:59:33.779763261 +0100 > > +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 2016-12-13 15:59:33.775763261 +0100 > > @@ -118,7 +118,7 @@ > > /* > > * When reaching cpu_alert3, reduce CPU > > * by 2 steps. On Exynos5422/5800 that would > > - * be: 1600 MHz and 1100 MHz. > > + * (usually) be: 1800 MHz and 1200 MHz. > > */ > > map3 { > > trip = <&cpu_alert3>; > > @@ -131,16 +131,16 @@ > > > > /* > > * When reaching cpu_alert4, reduce CPU > > - * further, down to 600 MHz (11 steps for big, > > - * 7 steps for LITTLE). > > + * further, down to 600 MHz (13 steps for big, > > + * 8 steps for LITTLE). > > */ > > - map5 { > > + cooling_map5: map5 { > > trip = <&cpu_alert4>; > > - cooling-device = <&cpu0 3 7>; > > + cooling-device = <&cpu0 3 8>; > > }; > > - map6 { > > + cooling_map6: map6 { > > trip = <&cpu_alert4>; > > - cooling-device = <&cpu4 3 11>; > > + cooling-device = <&cpu4 3 13>; > > }; > > }; > > }; > > Index: b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts > > =================================================================== > > --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts 2016-12-13 15:59:33.779763261 +0100 > > +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts 2016-12-13 15:59:33.775763261 +0100 > > @@ -21,6 +21,23 @@ > > compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; > > }; > > > > +&cluster_a15_opp_table { > > + /delete-node/opp@2000000000; > > + /delete-node/opp@1900000000; > > +}; > > + > > +&cluster_a7_opp_table { > > + /delete-node/opp@1400000000; > > +}; > > + > > I think that a comment in the DTS why these operating points aren't available > in this board will make more clear why the nodes are being deleted. Ok, I will add these comments in the next patch revision. > > +&cooling_map5 { > > + cooling-device = <&cpu0 3 7>; > > +}; > > + > > +&cooling_map6 { > > + cooling-device = <&cpu4 3 11>; > > +}; > > + > > &pwm { > > /* > > * PWM 0 -- fan > > Index: b/arch/arm/boot/dts/exynos5800-peach-pi.dts > > =================================================================== > > --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts 2016-12-13 15:59:33.779763261 +0100 > > +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts 2016-12-13 15:59:33.779763261 +0100 > > @@ -146,6 +146,10 @@ > > vdd-supply = <&ldo9_reg>; > > }; > > > > +&cluster_a7_opp_table { > > + /delete-property/opp@1400000000; > > +}; > > + > > &cpu0 { > > cpu-supply = <&buck2_reg>; > > }; > > Index: b/arch/arm/boot/dts/exynos5800.dtsi > > =================================================================== > > --- a/arch/arm/boot/dts/exynos5800.dtsi 2016-12-13 15:59:33.779763261 +0100 > > +++ b/arch/arm/boot/dts/exynos5800.dtsi 2016-12-13 15:59:33.779763261 +0100 > > @@ -24,6 +24,16 @@ > > }; > > > > &cluster_a15_opp_table { > > + opp@2000000000 { > > + opp-hz = /bits/ 64 <2000000000>; > > + opp-microvolt = <1250000>; > > + clock-latency-ns = <140000>; > > + }; > > + opp@1900000000 { > > + opp-hz = /bits/ 64 <1900000000>; > > + opp-microvolt = <1250000>; > > + clock-latency-ns = <140000>; > > + }; > > opp@1700000000 { > > opp-microvolt = <1250000>; > > }; > > @@ -85,6 +95,11 @@ > > }; > > > > AFAIK Thomas restricted the maximum OPP, because for A15 freqs > 1.8GHz the > INT rail would need to be scaled up as well since there's a maximum voltage > difference between the ARM and INT rails before the system becomes unstable: > > http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/276766.html > https://lkml.org/lkml/2014/5/2/419 > > The ChromiumOS vendor tree uses a virtual regulator driver that makes sure > the maximum voltage skew is between a limit. But that never made to mainline: > > https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.8/arch/arm/boot/dts/exynos5420-peach-pit.dtsi#90 > https://lkml.org/lkml/2014/4/29/28 > > Did that change and there's infrastructure in mainline now to cope with that? > If that's the case, I think it would be good to mention in the commit message. I was not aware of this limitation and AFAIK mainline has currently no code to handle it. I also cannot find any code to handle this in Hardkernel's vendor kernel for Odroid-XU3 board. Do you know whether this problem exists also on Exynos5422/5800 SoCs or only on Exynos5420 one? I see that ChromiumOS uses virtual regulator code also on Exynos5800 SoC based Peach Pi board but was the problem actually present on this board? [ I added Arjun to Cc:, maybe he can help in explaining this issue (unfortunately Inderpal's email is no longer working). ] Please also note that on Exynos5422/5800 SoCs the same ARM rail voltage is used for 1.9 GHz & 2.0 GHz OPPs as for the 1.8 GHz one. IOW if the problem exists it is already present in the mainline kernel. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics From mboxrd@z Thu Jan 1 00:00:00 1970 From: b.zolnierkie@samsung.com (Bartlomiej Zolnierkiewicz) Date: Wed, 14 Dec 2016 14:28:06 +0100 Subject: [PATCH] ARM: dts: Add missing CPU frequencies for Exynos5422/5800 In-Reply-To: <26ffeee4-ff43-b3d3-3267-5fcbc50e2974@osg.samsung.com> References: <5220084.l31t5oJbsy@amdc3058> <26ffeee4-ff43-b3d3-3267-5fcbc50e2974@osg.samsung.com> Message-ID: <2340115.HEG9AYUCMD@amdc3058> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tuesday, December 13, 2016 04:18:05 PM Javier Martinez Canillas wrote: > Hello Bartlomiej, Hi, > On 12/13/2016 01:52 PM, Bartlomiej Zolnierkiewicz wrote: > > Add missing 2000MHz & 1900MHz OPPs (for A15 cores) and 1400MHz OPP > > (for A7 cores). Also update common Odroid-XU3 Lite/XU3/XU4 thermal > > cooling maps to account for new OPPs. > > > > Since new OPPs are not available on all Exynos5422/5800 boards modify > > dts files for Odroid-XU3 Lite (limited to 1.8 GHz / 1.3 GHz) & Peach > > Pi (limited to 2.0 GHz / 1.3 GHz) accordingly. > > > > Tested on Odroid-XU3 and XU3 Lite. > > > > Cc: Doug Anderson > > Cc: Javier Martinez Canillas > > Cc: Andreas Faerber > > Cc: Thomas Abraham > > Cc: Ben Gamari > > Signed-off-by: Bartlomiej Zolnierkiewicz > > --- > > arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 14 +++++++------- > > arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 17 +++++++++++++++++ > > arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++++ > > arch/arm/boot/dts/exynos5800.dtsi | 15 +++++++++++++++ > > 4 files changed, 43 insertions(+), 7 deletions(-) > > > > Index: b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi > > =================================================================== > > --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 2016-12-13 15:59:33.779763261 +0100 > > +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 2016-12-13 15:59:33.775763261 +0100 > > @@ -118,7 +118,7 @@ > > /* > > * When reaching cpu_alert3, reduce CPU > > * by 2 steps. On Exynos5422/5800 that would > > - * be: 1600 MHz and 1100 MHz. > > + * (usually) be: 1800 MHz and 1200 MHz. > > */ > > map3 { > > trip = <&cpu_alert3>; > > @@ -131,16 +131,16 @@ > > > > /* > > * When reaching cpu_alert4, reduce CPU > > - * further, down to 600 MHz (11 steps for big, > > - * 7 steps for LITTLE). > > + * further, down to 600 MHz (13 steps for big, > > + * 8 steps for LITTLE). > > */ > > - map5 { > > + cooling_map5: map5 { > > trip = <&cpu_alert4>; > > - cooling-device = <&cpu0 3 7>; > > + cooling-device = <&cpu0 3 8>; > > }; > > - map6 { > > + cooling_map6: map6 { > > trip = <&cpu_alert4>; > > - cooling-device = <&cpu4 3 11>; > > + cooling-device = <&cpu4 3 13>; > > }; > > }; > > }; > > Index: b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts > > =================================================================== > > --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts 2016-12-13 15:59:33.779763261 +0100 > > +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts 2016-12-13 15:59:33.775763261 +0100 > > @@ -21,6 +21,23 @@ > > compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; > > }; > > > > +&cluster_a15_opp_table { > > + /delete-node/opp at 2000000000; > > + /delete-node/opp at 1900000000; > > +}; > > + > > +&cluster_a7_opp_table { > > + /delete-node/opp at 1400000000; > > +}; > > + > > I think that a comment in the DTS why these operating points aren't available > in this board will make more clear why the nodes are being deleted. Ok, I will add these comments in the next patch revision. > > +&cooling_map5 { > > + cooling-device = <&cpu0 3 7>; > > +}; > > + > > +&cooling_map6 { > > + cooling-device = <&cpu4 3 11>; > > +}; > > + > > &pwm { > > /* > > * PWM 0 -- fan > > Index: b/arch/arm/boot/dts/exynos5800-peach-pi.dts > > =================================================================== > > --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts 2016-12-13 15:59:33.779763261 +0100 > > +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts 2016-12-13 15:59:33.779763261 +0100 > > @@ -146,6 +146,10 @@ > > vdd-supply = <&ldo9_reg>; > > }; > > > > +&cluster_a7_opp_table { > > + /delete-property/opp at 1400000000; > > +}; > > + > > &cpu0 { > > cpu-supply = <&buck2_reg>; > > }; > > Index: b/arch/arm/boot/dts/exynos5800.dtsi > > =================================================================== > > --- a/arch/arm/boot/dts/exynos5800.dtsi 2016-12-13 15:59:33.779763261 +0100 > > +++ b/arch/arm/boot/dts/exynos5800.dtsi 2016-12-13 15:59:33.779763261 +0100 > > @@ -24,6 +24,16 @@ > > }; > > > > &cluster_a15_opp_table { > > + opp at 2000000000 { > > + opp-hz = /bits/ 64 <2000000000>; > > + opp-microvolt = <1250000>; > > + clock-latency-ns = <140000>; > > + }; > > + opp at 1900000000 { > > + opp-hz = /bits/ 64 <1900000000>; > > + opp-microvolt = <1250000>; > > + clock-latency-ns = <140000>; > > + }; > > opp at 1700000000 { > > opp-microvolt = <1250000>; > > }; > > @@ -85,6 +95,11 @@ > > }; > > > > AFAIK Thomas restricted the maximum OPP, because for A15 freqs > 1.8GHz the > INT rail would need to be scaled up as well since there's a maximum voltage > difference between the ARM and INT rails before the system becomes unstable: > > http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/276766.html > https://lkml.org/lkml/2014/5/2/419 > > The ChromiumOS vendor tree uses a virtual regulator driver that makes sure > the maximum voltage skew is between a limit. But that never made to mainline: > > https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.8/arch/arm/boot/dts/exynos5420-peach-pit.dtsi#90 > https://lkml.org/lkml/2014/4/29/28 > > Did that change and there's infrastructure in mainline now to cope with that? > If that's the case, I think it would be good to mention in the commit message. I was not aware of this limitation and AFAIK mainline has currently no code to handle it. I also cannot find any code to handle this in Hardkernel's vendor kernel for Odroid-XU3 board. Do you know whether this problem exists also on Exynos5422/5800 SoCs or only on Exynos5420 one? I see that ChromiumOS uses virtual regulator code also on Exynos5800 SoC based Peach Pi board but was the problem actually present on this board? [ I added Arjun to Cc:, maybe he can help in explaining this issue (unfortunately Inderpal's email is no longer working). ] Please also note that on Exynos5422/5800 SoCs the same ARM rail voltage is used for 1.9 GHz & 2.0 GHz OPPs as for the 1.8 GHz one. IOW if the problem exists it is already present in the mainline kernel. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics