From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37211) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d31oy-00077g-AJ for qemu-devel@nongnu.org; Tue, 25 Apr 2017 10:52:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d31ou-00045A-EV for qemu-devel@nongnu.org; Tue, 25 Apr 2017 10:52:04 -0400 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:35804) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d31ou-00044s-7z for qemu-devel@nongnu.org; Tue, 25 Apr 2017 10:52:00 -0400 Received: by mail-wr0-x243.google.com with SMTP id g12so7324662wrg.2 for ; Tue, 25 Apr 2017 07:52:00 -0700 (PDT) Sender: Richard Henderson References: <20170423215420.27098-1-shorne@gmail.com> <20170425141827.GA2724@lianli.shorne-pla.net> From: Richard Henderson Message-ID: <23c73add-77f3-f5c2-056f-0dc728a9027f@twiddle.net> Date: Tue, 25 Apr 2017 16:51:55 +0200 MIME-Version: 1.0 In-Reply-To: <20170425141827.GA2724@lianli.shorne-pla.net> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stafford Horne Cc: QEMU Development , Openrisc On 04/25/2017 04:18 PM, Stafford Horne wrote: > On Tue, Apr 25, 2017 at 12:11:00PM +0200, Richard Henderson wrote: >> On 04/23/2017 11:54 PM, Stafford Horne wrote: >>> The OpenRISC architecture has the Power Management Register (PMR) >>> special purpose register to manage cpu power states. The interesting >>> modes are: >>> >>> * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt >>> * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt >>> * Suspend Model (SUME) - Stop cpu and all units - wake on reset >>> >>> The linux kernel will set DME when idle. >> >> And SUME would be, essentially, poweroff? Perhaps at least for the purposes >> of QEMU; on real hardware one could press a button to assert reset and >> reboot. > > Yes, that is what I am thinking, but I could add this later, after some > reviews with other OpenRISC folks. > >>> Also, I don't know if its due to this patch of an issue with the timer >>> interrupts. After applying this patch the timer interrupts do not trigger >>> until a keypress is make. i.e. something like this... >>> >>> $ sleep 5 >>> >> ... >>> + cpu_restore_state(cs, GETPC() + 4); >> >> This isn't correct. You want >> >> cpu_restore_state(cs, GETPC()); >> cs->env.pc += 4; >> >> So what's happening is that you're re-executing the MTSPR and going back to >> sleep again. Which probably explains the hang. > > I have changed to the above, but I think its essentially the same. It > resumes after the MTSPR in both cases. It's not essentially the same. GETPC is a host address. Doing guest arithmetic on that is just wrong. > I fixed this now though, you should see another patch. The issue is the > timer events get ignored once the cpu is in halt state, I added a > qemu_cpu_kick() call in the timer hardware to wake up the cpu on timer > interrupts. Not sure if thats the best way to do it, but it works 100% > now. Ah, that could be. r~ From mboxrd@z Thu Jan 1 00:00:00 1970 From: Richard Henderson Date: Tue, 25 Apr 2017 16:51:55 +0200 Subject: [OpenRISC] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR In-Reply-To: <20170425141827.GA2724@lianli.shorne-pla.net> References: <20170423215420.27098-1-shorne@gmail.com> <20170425141827.GA2724@lianli.shorne-pla.net> Message-ID: <23c73add-77f3-f5c2-056f-0dc728a9027f@twiddle.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: openrisc@lists.librecores.org On 04/25/2017 04:18 PM, Stafford Horne wrote: > On Tue, Apr 25, 2017 at 12:11:00PM +0200, Richard Henderson wrote: >> On 04/23/2017 11:54 PM, Stafford Horne wrote: >>> The OpenRISC architecture has the Power Management Register (PMR) >>> special purpose register to manage cpu power states. The interesting >>> modes are: >>> >>> * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt >>> * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt >>> * Suspend Model (SUME) - Stop cpu and all units - wake on reset >>> >>> The linux kernel will set DME when idle. >> >> And SUME would be, essentially, poweroff? Perhaps at least for the purposes >> of QEMU; on real hardware one could press a button to assert reset and >> reboot. > > Yes, that is what I am thinking, but I could add this later, after some > reviews with other OpenRISC folks. > >>> Also, I don't know if its due to this patch of an issue with the timer >>> interrupts. After applying this patch the timer interrupts do not trigger >>> until a keypress is make. i.e. something like this... >>> >>> $ sleep 5 >>> >> ... >>> + cpu_restore_state(cs, GETPC() + 4); >> >> This isn't correct. You want >> >> cpu_restore_state(cs, GETPC()); >> cs->env.pc += 4; >> >> So what's happening is that you're re-executing the MTSPR and going back to >> sleep again. Which probably explains the hang. > > I have changed to the above, but I think its essentially the same. It > resumes after the MTSPR in both cases. It's not essentially the same. GETPC is a host address. Doing guest arithmetic on that is just wrong. > I fixed this now though, you should see another patch. The issue is the > timer events get ignored once the cpu is in halt state, I added a > qemu_cpu_kick() call in the timer hardware to wake up the cpu on timer > interrupts. Not sure if thats the best way to do it, but it works 100% > now. Ah, that could be. r~