From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38559) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aRrCW-0004SV-2n for qemu-devel@nongnu.org; Fri, 05 Feb 2016 19:58:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aRrCS-0001VT-SF for qemu-devel@nongnu.org; Fri, 05 Feb 2016 19:58:12 -0500 Received: from mail-bl2nam02on0051.outbound.protection.outlook.com ([104.47.38.51]:60320 helo=NAM02-BL2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aRrCS-0001VP-Mk for qemu-devel@nongnu.org; Fri, 05 Feb 2016 19:58:08 -0500 From: Alistair Francis Date: Fri, 5 Feb 2016 16:55:26 -0800 Message-ID: <24060e5dc8377b31c33a0e5f0ce6909910042aef.1454720021.git.alistair.francis@xilinx.com> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug feature register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alindsay@codeaurora.org, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, cov@codeaurora.org, nathan@nathanrossi.com The previously missing registers are now present in QEMU. Signed-off-by: Christopher Covington Signed-off-by: Alistair Francis --- target-arm/helper.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index b4bf6fa..1775768 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4267,12 +4267,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, - /* We mask out the PMUVer field, because we don't currently - * implement the PMU. Not advertising it prevents the guest - * from trying to use it and getting UNDEFs on registers we - * don't implement. - */ - .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, + .resetvalue = cpu->id_aa64dfr0 }, { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, -- 2.5.0