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Subject: Re: [RFC PATCH dev-5.1 3/6] irqchip/aspeed-i2c-ic: add I2C SRAM
 enabling control
To: Ryan Chen <ryan_chen@aspeedtech.com>,
 Brendan Higgins <brendanhiggins@google.com>,
 Benjamin Herrenschmidt <benh@kernel.crashing.org>,
 C?ric Le Goater <clg@kaod.org>, Joel Stanley <joel@jms.id.au>,
 Andrew Jeffery <andrew@aj.id.au>
Cc: "openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>
References: <20190620194922.15093-1-jae.hyun.yoo@linux.intel.com>
 <20190620194922.15093-4-jae.hyun.yoo@linux.intel.com>
 <c64ab19a31d1495f8e137d5ac58645b2@TWMBX02.aspeed.com>
From: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Message-ID: <2539f657-1966-c00d-dace-fa382bd1b85f@linux.intel.com>
Date: Fri, 21 Jun 2019 11:41:27 -0700
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On 6/20/2019 5:33 PM, Ryan Chen wrote:
> Hello Jae,
> 	The i2c register setting must after scu reset. - APEED_I2C_SRAM_BUFFER_EN
> 	My recommend aspeed-i2c-ic.c need be probe after scu reset. And all others i2c bus is no needed for scu reset.

Hello Ryan,

This module is registered after the SCU reset.
Thank you for the information.

Regards,
Jae

> 
> Ryan
> 
> -----Original Message-----
> From: openbmc [mailto:openbmc-bounces+ryan_chen=aspeedtech.com@lists.ozlabs.org] On Behalf Of Jae Hyun Yoo
> Sent: Friday, June 21, 2019 3:49 AM
> To: Brendan Higgins <brendanhiggins@google.com>; Benjamin Herrenschmidt <benh@kernel.crashing.org>; C?ric Le Goater <clg@kaod.org>; Joel Stanley <joel@jms.id.au>; Andrew Jeffery <andrew@aj.id.au>
> Cc: openbmc@lists.ozlabs.org; Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
> Subject: [RFC PATCH dev-5.1 3/6] irqchip/aspeed-i2c-ic: add I2C SRAM enabling control
> 
> This commit adds I2C SRAM enabling control for AST2500 SoC to support buffer mode and DMA mode transfer. The SRAM is enabled by default in AST2400 SoC.
> 
> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
> ---
>   drivers/irqchip/irq-aspeed-i2c-ic.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-aspeed-i2c-ic.c b/drivers/irqchip/irq-aspeed-i2c-ic.c
> index f20200af0992..99985b22a9fa 100644
> --- a/drivers/irqchip/irq-aspeed-i2c-ic.c
> +++ b/drivers/irqchip/irq-aspeed-i2c-ic.c
> @@ -18,6 +18,9 @@
>   #include <linux/of_irq.h>
>   #include <linux/io.h>
>   
> +/* I2C Global Control Register (AST2500) */
> +#define ASPEED_I2C_GLOBAL_CTRL_REG	0xc
> +#define  ASPEED_I2C_SRAM_BUFFER_EN	BIT(0)
>   
>   #define ASPEED_I2C_IC_NUM_BUS 14
>   
> @@ -100,6 +103,11 @@ static int __init aspeed_i2c_ic_of_init(struct device_node *node,
>   	irq_set_chained_handler_and_data(i2c_ic->parent_irq,
>   					 aspeed_i2c_ic_irq_handler, i2c_ic);
>   
> +	/* Enable I2C SRAM buffer in case of AST2500 */
> +	if (of_device_is_compatible(node, "aspeed,ast2500-i2c-ic"))
> +		writel(ASPEED_I2C_SRAM_BUFFER_EN,
> +		       i2c_ic->base + ASPEED_I2C_GLOBAL_CTRL_REG);
> +
>   	pr_info("i2c controller registered, irq %d\n", i2c_ic->parent_irq);
>   
>   	return 0;
> --
> 2.22.0
>