* [PATCH v2 1/2] dt-bindings: ufs: Add UFS platform driver for Cadence UFS
@ 2018-07-12 11:58 Janek Kotas
2018-07-16 16:11 ` Rob Herring
0 siblings, 1 reply; 3+ messages in thread
From: Janek Kotas @ 2018-07-12 11:58 UTC (permalink / raw)
To: robh+dt, mark.rutland, vinholikatti, jejb, martin.petersen
Cc: devicetree, linux-kernel, linux-scsi
This patch adds a device tree platform
driver description for Cadence UFS Controller.
Signed-off-by: Jan Kotas <jank@cadence.com>
---
.../devicetree/bindings/ufs/cdns,ufshc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
new file mode 100644
index 0000000..cb6d62a
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
@@ -0,0 +1,31 @@
+* Cadence Universal Flash Storage (UFS) Controller
+
+UFS nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible : compatible list, contains the following controller:
+ "cdns,ufshc"
+ complemented with the JEDEC version:
+ "jedec,ufs-2.0"
+
+- reg : address and length of the UFS register set
+- interrupts : one interrupt mapping
+- clocks : List of phandle and clock specifier pairs.
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property. "core" is mandatory.
+- freq-table-hz : Array of <min max> operating frequencies stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+
+Example:
+ ufs@fd030000 {
+ compatible = "cdns,ufshc", "jedec,ufs-2.0";
+ reg = <0xfd030000 0x10000>;
+ interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
+ freq-table-hz = <0 0>, <0 0>;
+ clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
+ clock-names = "core_clk", "phy_clk";
+ };
--
1.9.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: ufs: Add UFS platform driver for Cadence UFS
2018-07-12 11:58 [PATCH v2 1/2] dt-bindings: ufs: Add UFS platform driver for Cadence UFS Janek Kotas
@ 2018-07-16 16:11 ` Rob Herring
2018-07-25 13:47 ` Janek Kotas
0 siblings, 1 reply; 3+ messages in thread
From: Rob Herring @ 2018-07-16 16:11 UTC (permalink / raw)
To: Janek Kotas
Cc: mark.rutland, vinholikatti, jejb, martin.petersen, devicetree,
linux-kernel, linux-scsi
On Thu, Jul 12, 2018 at 11:58:04AM +0000, Janek Kotas wrote:
> This patch adds a device tree platform
> driver description for Cadence UFS Controller.
Bindings are not platform drivers...
>
> Signed-off-by: Jan Kotas <jank@cadence.com>
> ---
> .../devicetree/bindings/ufs/cdns,ufshc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
>
> diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
> new file mode 100644
> index 0000000..cb6d62a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
> @@ -0,0 +1,31 @@
> +* Cadence Universal Flash Storage (UFS) Controller
> +
> +UFS nodes are defined to describe on-chip UFS host controllers.
> +Each UFS controller instance should have its own node.
> +
> +Required properties:
> +- compatible : compatible list, contains the following controller:
> + "cdns,ufshc"
> + complemented with the JEDEC version:
> + "jedec,ufs-2.0"
> +
> +- reg : address and length of the UFS register set
> +- interrupts : one interrupt mapping
> +- clocks : List of phandle and clock specifier pairs.
> +- clock-names : List of clock input name strings sorted in the same
> + order as the clocks property. "core" is mandatory.
And phy?
> +- freq-table-hz : Array of <min max> operating frequencies stored in the same
> + order as the clocks property. If this property is not
> + defined or a value in the array is "0" then it is assumed
> + that the frequency is set by the parent clock or a
> + fixed rate clock source.
Don't define again here. Just refer to the common definition.
> +
> +Example:
> + ufs@fd030000 {
> + compatible = "cdns,ufshc", "jedec,ufs-2.0";
> + reg = <0xfd030000 0x10000>;
> + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
> + freq-table-hz = <0 0>, <0 0>;
> + clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
> + clock-names = "core_clk", "phy_clk";
Doesn't match the doc.
> + };
> --
> 1.9.0
>
> --
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: ufs: Add UFS platform driver for Cadence UFS
2018-07-16 16:11 ` Rob Herring
@ 2018-07-25 13:47 ` Janek Kotas
0 siblings, 0 replies; 3+ messages in thread
From: Janek Kotas @ 2018-07-25 13:47 UTC (permalink / raw)
To: Rob Herring; +Cc: devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2977 bytes --]
Thank you a lot for your comments,
I will fix these in the next version of the patch.
Jan
On 16 Jul 2018, at 18:11, Rob Herring <robh@kernel.org<mailto:robh@kernel.org>> wrote:
On Thu, Jul 12, 2018 at 11:58:04AM +0000, Janek Kotas wrote:
This patch adds a device tree platform
driver description for Cadence UFS Controller.
Bindings are not platform drivers…
OK, I will fix it.
Signed-off-by: Jan Kotas <jank@cadence.com<mailto:jank@cadence.com>>
---
.../devicetree/bindings/ufs/cdns,ufshc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
new file mode 100644
index 0000000..cb6d62a
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
@@ -0,0 +1,31 @@
+* Cadence Universal Flash Storage (UFS) Controller
+
+UFS nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible : compatible list, contains the following controller:
+ "cdns,ufshc"
+ complemented with the JEDEC version:
+ "jedec,ufs-2.0"
+
+- reg : address and length of the UFS register set
+- interrupts : one interrupt mapping
+- clocks : List of phandle and clock specifier pairs.
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property. "core" is mandatory.
And phy?
It depends on a type of the PHY. It’s not strictly needed by the driver.
In simulation and emulation, it’s possible to run a system without proper M-PHY.
I will clarify this.
+- freq-table-hz : Array of <min max> operating frequencies stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
Don't define again here. Just refer to the common definition.
OK, I will change that.
+
+Example:
+ ufs@fd030000 {
+ compatible = "cdns,ufshc", "jedec,ufs-2.0";
+ reg = <0xfd030000 0x10000>;
+ interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
+ freq-table-hz = <0 0>, <0 0>;
+ clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
+ clock-names = "core_clk", "phy_clk";
Doesn’t match the doc.
Thank you for spotting that, I will update the description.
+ };
--
1.9.0
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2018-07-12 11:58 [PATCH v2 1/2] dt-bindings: ufs: Add UFS platform driver for Cadence UFS Janek Kotas
2018-07-16 16:11 ` Rob Herring
2018-07-25 13:47 ` Janek Kotas
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