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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i24sm412944pfo.92.2020.03.01.20.28.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Mar 2020 20:28:57 -0800 (PST) Subject: Re: [RFC PATCH v2] target/ppc: Enable hardfloat for PPC To: Programmingkid , =?UTF-8?Q?Alex_Benn=c3=a9e?= , BALATON Zoltan References: <20200218171702.979F074637D@zero.eik.bme.hu> <1BC2E9E9-A694-4ED3-BD3D-D731F23B7245@gmail.com> <3539F747-145F-49CC-B494-C9794A8ABABA@gmail.com> <87eeuhxw0y.fsf@linaro.org> <878skpxltm.fsf@linaro.org> From: Richard Henderson Message-ID: <2576fd41-8b01-91a0-ca56-792ce65b5092@linaro.org> Date: Sun, 1 Mar 2020 20:28:55 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers , "qemu-ppc@nongnu.org" , Howard Spoelstra , luigi burdo , Dino Papararo , Aleksandar Markovic , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/1/20 4:13 PM, Programmingkid wrote: > Ok, I was just looking at Intel's x87 chip documentation. It supports IEEE 754 floating point operations and exception flags. This leads me to this question. Would simply taking the host exception flags and using them to set the PowerPC's FPU's flag be an acceptable solution to this problem? No. The primary issue is the FPSCR.FI flag. This is not an accumulative bit, per ieee754, but per operation. The "hardfloat" option works (with other targets) only with ieee745 accumulative exceptions, when the most common of those exceptions, inexact, has already been raised. And thus need not be raised a second time. Per the PowerPC architecture, inexact must be recognized afresh for every operation. Which is cheap in hardware but expensive in software. And once you're done with FI, FR has been and continues to be emulated incorrectly. r~