From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Ananyev, Konstantin" Subject: Re: [PATCH] lib: change rte_ring dequeue to guarantee ordering before tail update Date: Sat, 23 Jul 2016 11:15:27 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836B812E8@irsmsx105.ger.corp.intel.com> References: <20160715043951.32040-1-juhamatti.kuusisaari@coriant.com> <2601191342CEEE43887BDE71AB97725836B7E32F@irsmsx105.ger.corp.intel.com> <14017551.U6D1dIIx0P@xps13> <20160723060515.GA13747@localhost.localdomain> <20160723093621.GA18376@localhost.localdomain> <2601191342CEEE43887BDE71AB97725836B81292@irsmsx105.ger.corp.intel.com> <20160723103847.GB18376@localhost.localdomain> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: Thomas Monjalon , Juhamatti Kuusisaari , "dev@dpdk.org" To: Jerin Jacob Return-path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 425F8A10 for ; Sat, 23 Jul 2016 13:15:31 +0200 (CEST) In-Reply-To: <20160723103847.GB18376@localhost.localdomain> Content-Language: en-US List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Saturday, July 23, 2016 11:39 AM > To: Ananyev, Konstantin > Cc: Thomas Monjalon ; Juhamatti Kuusisaari ; dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH] lib: change rte_ring dequeue to guarantee= ordering before tail update >=20 > On Sat, Jul 23, 2016 at 10:14:51AM +0000, Ananyev, Konstantin wrote: > > Hi lads, > > > > > On Sat, Jul 23, 2016 at 11:02:33AM +0200, Thomas Monjalon wrote: > > > > 2016-07-23 8:05 GMT+02:00 Jerin Jacob : > > > > > On Thu, Jul 21, 2016 at 11:26:50PM +0200, Thomas Monjalon wrote: > > > > >> > > Consumer queue dequeuing must be guaranteed to be done > > > > >> > > fully before the tail is updated. This is not guaranteed > > > > >> > > with a read barrier, changed to a write barrier just before > > > > >> > > tail update which in > > > practice guarantees correct order of reads and writes. > > > > >> > > > > > > >> > > Signed-off-by: Juhamatti Kuusisaari > > > > >> > > > > > > >> > > > > > >> > Acked-by: Konstantin Ananyev > > > > >> > > > > >> Applied, thanks > > > > > > > > > > There was ongoing discussion on this > > > > > http://dpdk.org/ml/archives/dev/2016-July/044168.html > > > > > > > > Sorry Jerin, I forgot this email. > > > > The problem is that nobody replied to your email and you did not > > > > nack the v2 of this patch. > > > > It's probably my bad. > > I acked the patch before Jerin response, and forgot to reply later. > > > > > > > > > > > This change may not be required as it has the performance impact. > > > > > > > > We need to clearly understand what is the performance impact > > > > (numbers and use cases) on one hand, and is there a real bug fixed > > > > by this patch on the other hand? > > > > > > IHMO, there is no real bug here. rte_smb_rmb() provides the > > > LOAD-STORE barrier to make sure tail pointer WRITE happens only after= prior LOADS. > > > > Yep, from what I read at the link Jerin provided, indeed it seems rte_s= mp_rmb() is enough for the arm arch here... > > For ppc, as I can see both rte_smp_rmb()/rte_smp_wmb() emits the same i= nstruction. > > > > > > > > Thoughts? > > > > Wonder how big is a performance impact? >=20 > With this change we need to wait for addtional STORES to be completed to = local buffer in addtion to LOADS from ring buffers memory. I understand that, just wonder did you see any real performance difference? Probably with ring_perf_autotest/mempool_perf_autotest or something? Konstantin=20 >=20 > > If there is a real one, I suppose we can revert the patch? >=20 > Request to revert this one as their no benifts for other architectures an= d indeed it creates addtional delay in waiting for STORES to complete > in ARM. > Lets do the correct thing by reverting it. >=20 > Jerin >=20 >=20 >=20 > > Konstantin > > > > > > > > > > > > > Please guys make things clear and we'll revert if needed.