From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
Subject: Re: [PATCH v2] i40e: Fix eth_i40e_dev_init sequence
	on	ThunderX
Date: Sun, 20 Nov 2016 23:21:43 +0000
Message-ID: <2601191342CEEE43887BDE71AB9772583F0DE265@irsmsx105.ger.corp.intel.com>
References: <1479473533-9393-1-git-send-email-skoteshwar@caviumnetworks.com>
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Cc: "Wu, Jingjing" <jingjing.wu@intel.com>, "jerin.jacob@caviumnetworks.com"
 <jerin.jacob@caviumnetworks.com>, "jianbo.liu@linaro.org"
 <jianbo.liu@linaro.org>, "dev@dpdk.org" <dev@dpdk.org>
To: Satha Rao <skoteshwar@caviumnetworks.com>, "Zhang, Helin"
 <helin.zhang@intel.com>
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Hi
>=20
> i40e_asq_send_command: rd32 & wr32 under ThunderX gives unpredictable
>                        results. To solve this include rte memory barriers
>=20
> Signed-off-by: Satha Rao <skoteshwar@caviumnetworks.com>
> ---
>  drivers/net/i40e/base/i40e_osdep.h | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>=20
> diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i=
40e_osdep.h
> index 38e7ba5..ffa3160 100644
> --- a/drivers/net/i40e/base/i40e_osdep.h
> +++ b/drivers/net/i40e/base/i40e_osdep.h
> @@ -158,7 +158,13 @@ do {                                                =
            \
>  	((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
>  static inline uint32_t i40e_read_addr(volatile void *addr)
>  {
> +#if defined(RTE_ARCH_ARM64)
> +	uint32_t val =3D rte_le_to_cpu_32(I40E_PCI_REG(addr));
> +	rte_rmb();
> +	return val;

If you really need an rmb/wmb with MMIO read/writes on ARM,
I think you can avoid #ifdefs here and use rte_smp_rmb/rte_smp_wmb.
BTW, I suppose if you need it for i40e, you would need it for other devices=
 too.
Konstantin

> +#else
>  	return rte_le_to_cpu_32(I40E_PCI_REG(addr));
> +#endif
>  }
>  #define I40E_PCI_REG_WRITE(reg, value) \
>  	do { I40E_PCI_REG((reg)) =3D rte_cpu_to_le_32(value); } while (0)
> @@ -171,8 +177,16 @@ static inline uint32_t i40e_read_addr(volatile void =
*addr)
>  	I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value))
>=20
>  #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg)))
> +#if defined(RTE_ARCH_ARM64)
> +#define wr32(a, reg, value) \
> +	do { \
> +		I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value)); \
> +		rte_wmb(); \
> +	} while (0)
> +#else
>  #define wr32(a, reg, value) \
>  	I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value))
> +#endif
>  #define flush(a) i40e_read_addr(I40E_PCI_REG_ADDR((a), (I40E_GLGEN_STAT)=
))
>=20
>  #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
> --
> 2.7.4