From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Ananyev, Konstantin" Subject: Re: [PATCH] ring: relax alignment constraint on ring structure Date: Wed, 4 Apr 2018 23:38:41 +0000 Message-ID: <2601191342CEEE43887BDE71AB977258A0AB90E3@irsmsx105.ger.corp.intel.com> References: <20170630142609.6180-1-olivier.matz@6wind.com> <20180403132644.23729-1-olivier.matz@6wind.com> <20180403150722.GB15937@jerin> <20180403152517.hsjghkj5z6mauze7@platinum> <20180403153703.GA19072@jerin> <20180403155601.rqb7fhu6vggzrh7e@platinum> <20180403163254.GB19072@jerin> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: "dev@dpdk.org" , "Richardson, Bruce" To: Jerin Jacob , Olivier Matz Return-path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id E04E01C8E2 for ; Thu, 5 Apr 2018 01:38:44 +0200 (CEST) In-Reply-To: <20180403163254.GB19072@jerin> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi lads, > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Tuesday, April 3, 2018 5:43 PM > To: Olivier Matz > Cc: dev@dpdk.org; Ananyev, Konstantin ; Ric= hardson, Bruce > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring = structure >=20 > -----Original Message----- > > Date: Tue, 3 Apr 2018 17:56:01 +0200 > > From: Olivier Matz > > To: Jerin Jacob > > CC: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.= com > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on rin= g > > structure > > User-Agent: NeoMutt/20170113 (1.7.2) > > > > On Tue, Apr 03, 2018 at 09:07:04PM +0530, Jerin Jacob wrote: > > > -----Original Message----- > > > > Date: Tue, 3 Apr 2018 17:25:17 +0200 > > > > From: Olivier Matz > > > > To: Jerin Jacob > > > > CC: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@in= tel.com > > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on= ring > > > > structure > > > > User-Agent: NeoMutt/20170113 (1.7.2) > > > > > > > > On Tue, Apr 03, 2018 at 08:37:23PM +0530, Jerin Jacob wrote: > > > > > -----Original Message----- > > > > > > Date: Tue, 3 Apr 2018 15:26:44 +0200 > > > > > > From: Olivier Matz > > > > > > To: dev@dpdk.org > > > > > > Subject: [dpdk-dev] [PATCH] ring: relax alignment constraint on= ring > > > > > > structure > > > > > > X-Mailer: git-send-email 2.11.0 > > > > > > > > > > > > The initial objective of > > > > > > commit d9f0d3a1ffd4 ("ring: remove split cacheline build settin= g") > > > > > > was to add an empty cache line betwee, the producer and consume= r > > > > > > data (on platform with cache line size =3D 64B), preventing fro= m > > > > > > having them on adjacent cache lines. > > > > > > > > > > > > Following discussion on the mailing list, it appears that this > > > > > > also imposes an alignment constraint that is not required. > > > > > > > > > > > > This patch removes the extra alignment constraint and adds the > > > > > > empty cache lines using padding fields in the structure. The > > > > > > size of rte_ring structure and the offset of the fields remain > > > > > > the same on platforms with cache line size =3D 64B: > > > > > > > > > > > > rte_ring =3D 384 > > > > > > rte_ring.name =3D 0 > > > > > > rte_ring.flags =3D 32 > > > > > > rte_ring.memzone =3D 40 > > > > > > rte_ring.size =3D 48 > > > > > > rte_ring.mask =3D 52 > > > > > > rte_ring.prod =3D 128 > > > > > > rte_ring.cons =3D 256 > > > > > > > > > > > > But it has an impact on platform where cache line size is 128B: > > > > > > > > > > > > rte_ring =3D 384 -> 768 > > > > > > rte_ring.name =3D 0 > > > > > > rte_ring.flags =3D 32 > > > > > > rte_ring.memzone =3D 40 > > > > > > rte_ring.size =3D 48 > > > > > > rte_ring.mask =3D 52 > > > > > > rte_ring.prod =3D 128 -> 256 > > > > > > rte_ring.cons =3D 256 -> 512 > > > > > > > > > > Are we leaving TWO cacheline to make sure, HW prefetch don't load > > > > > the adjust cacheline(consumer)? > > > > > > > > > > If so, Will it have impact on those machine where it is 128B Cach= e line > > > > > and the HW prefetcher is not loading the next caching explicitly.= Right? > > > > > > > > The impact on machines that have a 128B cache line is that an unuse= d > > > > cache line will be added between the producer and consumer data. I > > > > expect that the impact is positive in case there is a hw prefetcher= , and > > > > null in case there is no such prefetcher. > > > > > > It is not NULL, Right? You are loosing 256B for each ring. > > > > Is it really that important? >=20 > Pipeline or eventdev SW cases there could more rings in the system. > I don't see any downside of having config option which is enabled > default. >=20 > In my view, such config options are good, as in embedded usecases, custom= ers > can really fine tune the target for the need. In server usecases, let the= default > of option be enabled, no harm. But that would mean we have to maintain two layouts for the rte_ring struct= ure. I am agree with Olivier here, might be saving 256B per ring is not worth su= ch hassle. Konstantin >=20 > > > > > > > > On machines with 64B cache line, this was already the case. It just > > > > reduces the alignment constraint. > > > > > > Not all the 64B CL machines will have HW prefetch. > > > > > > I would recommend to add conditional compilation flags to express HW > > > prefetch enabled or not? based on that we can decide to reserve > > > the additional space. By default, in common config, HW prefetch can > > > be enabled so that it works for almost all cases. > > > > The hw prefetcher can be enabled at runtime, so a compilation flag > > does not seem to be a good idea. Moreover, changing this compilation >=20 > On those Hardwares HW prefetch can be disabled at runtime, it is fine > with default config. I was taking about some low end ARM hardware which > does not have HW prefetch is not present at all. >=20 > > flag would change the ABI. >=20 > ABI is broken anyway, Right? due to size of the structure change. >=20