From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Ananyev, Konstantin" Subject: Re: [PATCH] ring: relax alignment constraint on ring structure Date: Wed, 11 Apr 2018 08:40:32 +0000 Message-ID: <2601191342CEEE43887BDE71AB977258AE913720@IRSMSX102.ger.corp.intel.com> References: <20180403150722.GB15937@jerin> <20180403152517.hsjghkj5z6mauze7@platinum> <20180403153703.GA19072@jerin> <20180403155601.rqb7fhu6vggzrh7e@platinum> <20180403163254.GB19072@jerin> <2601191342CEEE43887BDE71AB977258A0AB90E3@irsmsx105.ger.corp.intel.com> <20180405080134.GA2674@jerin> <2601191342CEEE43887BDE71AB977258A0AB9930@irsmsx105.ger.corp.intel.com> <20180406012624.GA12155@jerin> <2601191342CEEE43887BDE71AB977258AE913464@IRSMSX102.ger.corp.intel.com> <20180411024845.GA5049@jerin> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: Olivier Matz , "dev@dpdk.org" , "Richardson, Bruce" To: Jerin Jacob Return-path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id A1A841BAAC for ; Wed, 11 Apr 2018 10:40:36 +0200 (CEST) In-Reply-To: <20180411024845.GA5049@jerin> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Jerin, > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Wednesday, April 11, 2018 3:49 AM > To: Ananyev, Konstantin > Cc: Olivier Matz ; dev@dpdk.org; Richardson, Bruc= e > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring = structure >=20 > -----Original Message----- > > Date: Wed, 11 Apr 2018 00:33:14 +0000 > > From: "Ananyev, Konstantin" > > To: Jerin Jacob > > CC: Olivier Matz , "dev@dpdk.org" , > > "Richardson, Bruce" > > Subject: RE: [dpdk-dev] [PATCH] ring: relax alignment constraint on rin= g > > structure > > >=20 > Hi Konstantin, >=20 > > > > > -----Original Message----- > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > Sent: Friday, April 6, 2018 2:26 AM > > > To: Ananyev, Konstantin > > > Cc: Olivier Matz ; dev@dpdk.org; Richardson, = Bruce > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on r= ing structure > > > > > > -----Original Message----- > > > > > > Hi Konstantin, > > > > > > > > > > > > -----Original Message----- > > > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > > > Sent: Thursday, April 5, 2018 9:02 AM > > > > > To: Ananyev, Konstantin > > > > > Cc: Olivier Matz ; dev@dpdk.org; Richards= on, Bruce > > > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint = on ring structure > > > > > > > > > > -----Original Message----- > > > > > > Date: Wed, 4 Apr 2018 23:38:41 +0000 > > > > > > From: "Ananyev, Konstantin" > > > > > > To: Jerin Jacob , Olivier Matz > > > > > > > > > > > > CC: "dev@dpdk.org" , "Richardson, Bruce" > > > > > > > > > > > > Subject: RE: [dpdk-dev] [PATCH] ring: relax alignment constrain= t on ring > > > > > > structure > > > > > > > > > > > > Hi lads, > > > > > > > > > > > > > -----Original Message----- > > > > > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > > > > > Sent: Tuesday, April 3, 2018 5:43 PM > > > > > > > To: Olivier Matz > > > > > > > Cc: dev@dpdk.org; Ananyev, Konstantin ; Richardson, Bruce > > > > > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constra= int on ring structure > > > > > > > > > > > > > > -----Original Message----- > > > > > > > > Date: Tue, 3 Apr 2018 17:56:01 +0200 > > > > > > > > From: Olivier Matz > > > > > > > > To: Jerin Jacob > > > > > > > > CC: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richa= rdson@intel.com > > > > > > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment const= raint on ring > > > > > > > > structure > > > > > > > > User-Agent: NeoMutt/20170113 (1.7.2) > > > > > > > > > > > > > > > > On Tue, Apr 03, 2018 at 09:07:04PM +0530, Jerin Jacob wrote= : > > > > > > > > > -----Original Message----- > > > > > > > > > > Date: Tue, 3 Apr 2018 17:25:17 +0200 > > > > > > > > > > From: Olivier Matz > > > > > > > > > > To: Jerin Jacob > > > > > > > > > > CC: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.r= ichardson@intel.com > > > > > > > > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment c= onstraint on ring > > > > > > > > > > structure > > > > > > > > > > User-Agent: NeoMutt/20170113 (1.7.2) > > > > > > > > > > > > > > > > > > > > On Tue, Apr 03, 2018 at 08:37:23PM +0530, Jerin Jacob w= rote: > > > > > > > > > > > -----Original Message----- > > > > > > > > > > > > Date: Tue, 3 Apr 2018 15:26:44 +0200 > > > > > > > > > > > > From: Olivier Matz > > > > > > > > > > > > To: dev@dpdk.org > > > > > > > > > > > > Subject: [dpdk-dev] [PATCH] ring: relax alignment c= onstraint on ring > > > > > > > > > > > > structure > > > > > > > > > > > > X-Mailer: git-send-email 2.11.0 > > > > > > > > > > > > > > > > > > > > > > > > The initial objective of > > > > > > > > > > > > commit d9f0d3a1ffd4 ("ring: remove split cacheline = build setting") > > > > > > > > > > > > was to add an empty cache line betwee, the producer= and consumer > > > > > > > > > > > > data (on platform with cache line size =3D 64B), pr= eventing from > > > > > > > > > > > > having them on adjacent cache lines. > > > > > > > > > > > > > > > > > > > > > > > > Following discussion on the mailing list, it appear= s that this > > > > > > > > > > > > also imposes an alignment constraint that is not re= quired. > > > > > > > > > > > > > > > > > > > > > > > > This patch removes the extra alignment constraint a= nd adds the > > > > > > > > > > > > empty cache lines using padding fields in the struc= ture. The > > > > > > > > > > > > size of rte_ring structure and the offset of the fi= elds remain > > > > > > > > > > > > the same on platforms with cache line size =3D 64B: > > > > > > > > > > > > > > > > > > > > > > > > rte_ring =3D 384 > > > > > > > > > > > > rte_ring.name =3D 0 > > > > > > > > > > > > rte_ring.flags =3D 32 > > > > > > > > > > > > rte_ring.memzone =3D 40 > > > > > > > > > > > > rte_ring.size =3D 48 > > > > > > > > > > > > rte_ring.mask =3D 52 > > > > > > > > > > > > rte_ring.prod =3D 128 > > > > > > > > > > > > rte_ring.cons =3D 256 > > > > > > > > > > > > > > > > > > > > > > > > But it has an impact on platform where cache line s= ize is 128B: > > > > > > > > > > > > > > > > > > > > > > > > rte_ring =3D 384 -> 768 > > > > > > > > > > > > rte_ring.name =3D 0 > > > > > > > > > > > > rte_ring.flags =3D 32 > > > > > > > > > > > > rte_ring.memzone =3D 40 > > > > > > > > > > > > rte_ring.size =3D 48 > > > > > > > > > > > > rte_ring.mask =3D 52 > > > > > > > > > > > > rte_ring.prod =3D 128 -> 256 > > > > > > > > > > > > rte_ring.cons =3D 256 -> 512 > > > > > > > > > > > > > > > > > > > > > > Are we leaving TWO cacheline to make sure, HW prefetc= h don't load > > > > > > > > > > > the adjust cacheline(consumer)? > > > > > > > > > > > > > > > > > > > > > > If so, Will it have impact on those machine where it = is 128B Cache line > > > > > > > > > > > and the HW prefetcher is not loading the next caching= explicitly. Right? > > > > > > > > > > > > > > > > > > > > The impact on machines that have a 128B cache line is t= hat an unused > > > > > > > > > > cache line will be added between the producer and consu= mer data. I > > > > > > > > > > expect that the impact is positive in case there is a h= w prefetcher, and > > > > > > > > > > null in case there is no such prefetcher. > > > > > > > > > > > > > > > > > > It is not NULL, Right? You are loosing 256B for each ring= . > > > > > > > > > > > > > > > > Is it really that important? > > > > > > > > > > > > > > Pipeline or eventdev SW cases there could more rings in the s= ystem. > > > > > > > I don't see any downside of having config option which is ena= bled > > > > > > > default. > > > > > > > > > > > > > > In my view, such config options are good, as in embedded usec= ases, customers > > > > > > > can really fine tune the target for the need. In server useca= ses, let the default > > > > > > > of option be enabled, no harm. > > > > > > > > > > > > But that would mean we have to maintain two layouts for the rte= _ring structure. > > > > > > > > > > Is there any downside of having two configurable layout? meaning,= we are not > > > > > transferring rte_ring structure over network etc(ie no interopera= bility > > > > > issue). Does it really matter? May I am missing something here. > > > > > > > > My concern about potential compatibility problems we are introducin= g - > > > > library build with 'y', while app wit 'n', or visa-versa. > > > > > > Got it. > > > > > > > I wonder are there really a lot of users who would be interested in= such savings? > > > > Could it happen that this new option would sit here unused and unte= sted? > > > > > > OK. Fair enough. I have no objections for Olivier patch. > > > > > > As a suggestion, may be we can move "char name[RTE_MEMZONE_NAMESIZE]"= in the > > > struct rte_ring in place of " empty cacheline" to save 32B. No strong= option > > > though. > > > > That sounds like a good idea to me... > > But I suppose in that case we need to move to that empty cacheline all = fields that precede prod? >=20 > Even though those fields are read only in fastpath,I suppose moving all > the fields(used in fast path) after prod, prefetch _cons_ cache line in c= ross > CPU case. Ah yes, you right, missed that. Konstantin >=20 > I think, following comment can be addressed in code as it is an ABI chang= e. > /* > * Note: this field kept the RTE_MEMZONE_NAMESIZE size due to > * ABI > * compatibility requirements, it could be changed to > * RTE_RING_NAMESIZE > * next time the ABI changes > */ > char name[RTE_MEMZONE_NAMESIZE] __rte_cache_aligned; /**< Name of= the ring. */ >=20 >=20 > > Otherwise there will be not much advantage in such move. > > > >