From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80A70C3A5A9 for ; Tue, 5 May 2020 01:06:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D687206C0 for ; Tue, 5 May 2020 01:06:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5D687206C0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=whitecape.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0015B89CF8; Tue, 5 May 2020 01:06:52 +0000 (UTC) X-Greylist: delayed 581 seconds by postgrey-1.36 at gabe; Tue, 05 May 2020 01:06:51 UTC Received: from smtp90.iad3b.emailsrvr.com (smtp90.iad3b.emailsrvr.com [146.20.161.90]) by gabe.freedesktop.org (Postfix) with ESMTPS id A09B989CF8 for ; Tue, 5 May 2020 01:06:51 +0000 (UTC) X-Auth-ID: kenneth@whitecape.org Received: by smtp12.relay.iad3b.emailsrvr.com (Authenticated sender: kenneth-AT-whitecape.org) with ESMTPSA id 83726C0133; Mon, 4 May 2020 20:57:09 -0400 (EDT) X-Sender-Id: kenneth@whitecape.org Received: from mizzik.localnet (50-39-162-34.bvtn.or.frontiernet.net [50.39.162.34]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:465 (trex/5.7.12); Mon, 04 May 2020 20:57:09 -0400 From: Kenneth Graunke To: intel-gfx@lists.freedesktop.org, D Scott Phillips Date: Mon, 04 May 2020 17:57:05 -0700 Message-ID: <2650835.mvXUDI8C0e@mizzik> In-Reply-To: <20200505000146.2295525-1-d.scott.phillips@intel.com> References: <20200505000146.2295525-1-d.scott.phillips@intel.com> MIME-Version: 1.0 X-Classification-ID: e6077747-36d2-49b6-9974-5b775c7eeadd-1-1 Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Content-Type: multipart/mixed; boundary="===============0915026900==" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --===============0915026900== Content-Type: multipart/signed; boundary="nextPart11637060.O9o76ZdvQC"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPart11637060.O9o76ZdvQC Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" On Monday, May 4, 2020 5:01:46 PM PDT D Scott Phillips wrote: > Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12 > pipe_control commands. HDC Pipeline flush actually resides in > dword 0, and the bit we were setting in dword 1 was Indirect State > Pointers Disable, which invalidates indirect state in the render > context. This causes failures for userspace, as things like push > constant state gets invalidated. > > Cc: Mika Kuoppala > Cc: Chris Wilson > Signed-off-by: D Scott Phillips > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 23 +++++++++++++++++------ > drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++++++----- > 2 files changed, 23 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 19d0b8830905..8338be338ec8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); > void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine, > struct drm_printer *p); > > -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) > +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset) Great find! It looks like HDC_PIPELINE_FLUSH moved from bit 41 to bit 9 even on Icelake / Gen11 - so it might make sense to call this gen11_emit_pipe_control() and use it on the Icelake functions. That said, i915 never sets HDC_PIPELINE_FLUSH until Gen12, so we don't actually have a bug to fix on Icelake today. But if someone started trying to set it on Gen11, we would have a bug - hence the suggestion. With or without any changes, Reviewed-by: Kenneth Graunke and thanks so much for tracking this down! --nextPart11637060.O9o76ZdvQC Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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