From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Wed, 22 Mar 2017 09:41:06 +0100 Subject: [U-Boot] [PATCH v2 15/20] arm: socfpga: Add SPL support for Arria 10 In-Reply-To: References: <1489019218-4071-1-git-send-email-ley.foon.tan@intel.com> <1489019218-4071-16-git-send-email-ley.foon.tan@intel.com> Message-ID: <26d704e4-26ff-3b38-f2d5-47db6d8a296c@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/22/2017 09:28 AM, Ley Foon Tan wrote: > On Fri, Mar 10, 2017 at 9:52 AM, Marek Vasut wrote: >> On 03/09/2017 01:26 AM, Ley Foon Tan wrote: >>> Add SPL support for Arria 10 and add reset_uart() to use in SPL. >>> >>> Signed-off-by: Tien Fong Chee >>> Signed-off-by: Ley Foon Tan >>> --- >>> .../include/mach/reset_manager_arria10.h | 1 + >>> arch/arm/mach-socfpga/reset_manager_arria10.c | 18 +++++++ >>> arch/arm/mach-socfpga/spl.c | 55 +++++++++++++++++++++- >>> 3 files changed, 72 insertions(+), 2 deletions(-) >>> >>> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h >>> index e3171d1..d0711cf 100644 >>> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h >>> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h >>> @@ -14,6 +14,7 @@ void emac_manage_reset(ulong emacbase, uint state); >>> int reset_deassert_bridges_handoff(void); >>> void reset_assert_fpga_connected_peripherals(void); >>> void reset_deassert_osc1wd0(void); >>> +void reset_uart(int assert); >>> >>> struct socfpga_reset_manager { >>> u32 stat; >>> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c >>> index 547a8bb..bbf54f0 100644 >>> --- a/arch/arm/mach-socfpga/reset_manager_arria10.c >>> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c >>> @@ -28,6 +28,24 @@ static const struct socfpga_system_manager *sysmgr_regs = >>> ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \ >>> ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK) >> >> Should be part of reset manager patch ... > Do you mean by the reset_uart() below? In the last review, you comment > that uart_com_port() is in later patch (misc path) of reset manager > patch. So, I moved this function to this here. Let me know if you > prefer a new patch this reset_uart(). It just doesn't seem right to have reset-manager code bits in SPL patch, that's all . Do you mean you have the uart_com_port() function in misc.c and this reset manager bit depends on it ? Then swap patches 3 and 4 and you can wrap this function into the reset manager part, no? >>> +void reset_uart(int assert) >>> +{ >>> + u32 mask = 0; >>> + unsigned int com_port; >>> + >>> + com_port = uart_com_port(gd->fdt_blob); >>> + >>> + if (com_port == SOCFPGA_UART1_ADDRESS) >>> + mask |= ALT_RSTMGR_PER1MODRST_UART1_SET_MSK; >>> + else if (com_port == SOCFPGA_UART0_ADDRESS) >>> + mask |= ALT_RSTMGR_PER1MODRST_UART0_SET_MSK; >>> + >>> + if (assert) >>> + setbits_le32(&reset_manager_base->per1modrst, mask); >>> + else >>> + clrbits_le32(&reset_manager_base->per1modrst, mask); >>> +} >>> + [...] -- Best regards, Marek Vasut