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From: Dmitry Osipenko <digetx@gmail.com>
To: Ashish Mhetre <amhetre@nvidia.com>,
	krzysztof.kozlowski@canonical.com, robh+dt@kernel.org,
	thierry.reding@gmail.com, jonathanh@nvidia.com,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org
Cc: vdumpa@nvidia.com, Snikam@nvidia.com
Subject: Re: [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186
Date: Sat, 19 Mar 2022 18:42:35 +0300	[thread overview]
Message-ID: <274dc445-b2c2-9a3a-df04-ded95f2223ad@gmail.com> (raw)
In-Reply-To: <20220316092525.4554-4-amhetre@nvidia.com>

16.03.2022 12:25, Ashish Mhetre пишет:
> From tegra186 onwards, memory controller support multiple channels.
> Reg items are updated with address and size of these channels.
> Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234
> have overall 17 memory controller channels each.
> There is 1 reg item for memory controller stream-id registers.
> So update the reg maxItems to 18 in tegra186 devicetree documentation.
> 
> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
> ---
>  .../nvidia,tegra186-mc.yaml                   | 20 +++++++++++++------
>  1 file changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> index 13c4c82fd0d3..3c4e231dc1de 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> @@ -34,8 +34,8 @@ properties:
>            - nvidia,tegra234-mc
>  
>    reg:
> -    minItems: 1
> -    maxItems: 3
> +    minItems: 6
> +    maxItems: 18
>  
>    interrupts:
>      items:
> @@ -142,7 +142,8 @@ allOf:
>      then:
>        properties:
>          reg:
> -          maxItems: 1
> +          maxItems: 6
> +          description: 5 memory controller channels and 1 for stream-id registers
>  
>    - if:
>        properties:
> @@ -151,7 +152,8 @@ allOf:
>      then:
>        properties:
>          reg:
> -          minItems: 3
> +          minItems: 18
> +          description: 17 memory controller channels and 1 for stream-id registers
>  
>    - if:
>        properties:
> @@ -160,7 +162,8 @@ allOf:
>      then:
>        properties:
>          reg:
> -          minItems: 3
> +          minItems: 18
> +          description: 17 memory controller channels and 1 for stream-id registers
>  
>  additionalProperties: false
>  
> @@ -198,7 +201,12 @@ examples:
>  
>              external-memory-controller@2c60000 {
>                  compatible = "nvidia,tegra186-emc";
> -                reg = <0x0 0x02c60000 0x0 0x50000>;
> +                reg = <0x0 0x02c00000 0x0 0x10000>,    /* MC-SID */
> +                      <0x0 0x02c10000 0x0 0x10000>,    /* Broadcast channel */
> +                      <0x0 0x02c20000 0x0 0x10000>,    /* MC0 */
> +                      <0x0 0x02c30000 0x0 0x10000>,    /* MC1 */
> +                      <0x0 0x02c40000 0x0 0x10000>,    /* MC2 */
> +                      <0x0 0x02c50000 0x0 0x10000>;    /* MC3 */
>                  interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
>                  clocks = <&bpmp TEGRA186_CLK_EMC>;
>                  clock-names = "emc";

This is the EMC node, not MC.

  reply	other threads:[~2022-03-19 15:42 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-16  9:25 [Patch v5 0/4] memory: tegra: Add MC channels and error logging Ashish Mhetre
2022-03-16  9:25 ` [Patch v5 1/4] memory: tegra: Add memory controller channels support Ashish Mhetre
2022-03-19 15:42   ` Dmitry Osipenko
2022-03-22 16:13     ` Ashish Mhetre
2022-03-25  4:50     ` Ashish Mhetre
2022-03-29 23:48       ` Dmitry Osipenko
2022-03-30  5:07         ` Ashish Mhetre
2022-03-20 12:31   ` Krzysztof Kozlowski
2022-03-22 18:04     ` Ashish Mhetre
2022-03-22 18:24       ` Krzysztof Kozlowski
2022-03-16  9:25 ` [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward Ashish Mhetre
2022-03-19 15:50   ` Dmitry Osipenko
2022-03-19 16:19     ` Dmitry Osipenko
2022-03-22 17:51       ` Ashish Mhetre
2022-03-22 16:48     ` Ashish Mhetre
2022-03-19 15:59   ` Dmitry Osipenko
2022-03-22 17:23     ` Ashish Mhetre
2022-03-29 23:51       ` Dmitry Osipenko
2022-03-30  5:02         ` Ashish Mhetre
2022-03-19 16:14   ` Dmitry Osipenko
2022-03-22 17:34     ` Ashish Mhetre
2022-03-30  0:01       ` Dmitry Osipenko
2022-03-30 10:16         ` Ashish Mhetre
2022-03-30 10:36           ` Dmitry Osipenko
2022-03-30 11:22             ` Ashish Mhetre
2022-03-31 19:49               ` Dmitry Osipenko
2022-03-31 21:55                 ` Ashish Mhetre
2022-03-20 12:53   ` Dmitry Osipenko
2022-03-23  8:36     ` Ashish Mhetre
2022-03-30  0:06   ` Dmitry Osipenko
2022-03-30  9:03     ` Ashish Mhetre
2022-03-30 10:19       ` Dmitry Osipenko
2022-03-30 10:34         ` Ashish Mhetre
2022-03-16  9:25 ` [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186 Ashish Mhetre
2022-03-19 15:42   ` Dmitry Osipenko [this message]
2022-03-20  2:13   ` Rob Herring
2022-03-20 12:42   ` Krzysztof Kozlowski
2022-03-22 18:12     ` Ashish Mhetre
2022-03-22 18:42       ` Krzysztof Kozlowski
2022-03-16  9:25 ` [Patch v5 4/4] arm64: tegra: Add memory controller channels Ashish Mhetre

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