From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 161BAC433B4 for ; Wed, 21 Apr 2021 08:31:43 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id 7795761449 for ; Wed, 21 Apr 2021 08:31:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7795761449 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA4DB419D0; Wed, 21 Apr 2021 10:31:40 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 21DB94195D for ; Wed, 21 Apr 2021 10:31:38 +0200 (CEST) IronPort-SDR: 5+/8GolP+6KVOPjGaAR8gnLf2m8w8KMw1zZwFVurDZRdWcAxDj0uKHy6MmtqcPD0LWTlbgZZRY 1uqy7V4yN2bg== X-IronPort-AV: E=McAfee;i="6200,9189,9960"; a="195218010" X-IronPort-AV: E=Sophos;i="5.82,238,1613462400"; d="scan'208";a="195218010" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2021 01:31:37 -0700 IronPort-SDR: Jh3W8sew5k8KA3osOQFdVvby1Ab5GKPmrtNvUKk6Vs1eWZZZEejBreEccaCo3xGnT8TMNslxF+ 6On7mcGNcV8g== X-IronPort-AV: E=Sophos;i="5.82,238,1613462400"; d="scan'208";a="455246959" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.206.218]) ([10.213.206.218]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2021 01:31:36 -0700 To: Jiawei Wang , matan@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com, thomas@monjalon.net Cc: dev@dpdk.org, rasland@nvidia.com, asafp@nvidia.com References: <20210331073632.1443011-1-lizh@nvidia.com> <1618916122-181792-1-git-send-email-jiaweiw@nvidia.com> From: Ferruh Yigit X-User: ferruhy Message-ID: <2783b22f-aff2-28d6-71dd-8e0725bf499f@intel.com> Date: Wed, 21 Apr 2021 09:31:32 +0100 MIME-Version: 1.0 In-Reply-To: <1618916122-181792-1-git-send-email-jiaweiw@nvidia.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v6 00/15] Add ASO meter support in MLX5 PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 4/20/2021 11:55 AM, Jiawei Wang wrote: > To support more meters and better performance, > MLX HW provides ASO (Advanced Steering Operation) flow meter. > It can expose millions of ASO flow meter context's in HW. > This ASO object can allocate the large bulk meter objects. > This patch set implement the ASO flow meter for mlx5 driver. > MLX5 PMD driver will be responsible for ASO flow meter manage to HW. > > V2: Fix compile error issue (mlx5_glue->destroy_flow_action) > V3: Fix comments. > V4: Fix comments and add Acked. > V5: Fix unused log_obj_size issue. > V6: Fix comments and update release notes. > > Jiawei Wang (1): > doc: update release notes for ASO meter > > Li Zhang (10): > net/mlx5: optimize meter statistics > common/mlx5: add definitions for ASO flow meter > common/mlx5: add read ASO flow meter HCA capability > common/mlx5: add DevX API to create ASO flow meter object > net/mlx5: flow meter pool to manage meter object > net/mlx5: initialize the flow meter ASO SQ > net/mlx5: add meter ASO queue management > net/mlx5: add support of ASO meter action > net/mlx5: make ASO meter queue thread-safe > net/mlx5: allow multiple flow tables on the same level > > Shun Hao (3): > common/mlx5: add color register idle bits definition > net/mlx5: fix meter statistics > net/mlx5: use mask for meter register setting > > Suanming Mou (1): > net/mlx5: support three level table walk > Hi Li, The request in previous patch was to add some documentation on the new feature in driver documentation, plus some design documentation if needed, not just release notes update. But this patch become on the critical path for -rc1, since an mlx ethdev patch depends on this patch, I want to block them for the release, instead does it make sense the have the documentation update for the -rc2, what do you think? Thanks, ferruh