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From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,
	ville.syrjala@linux.intel.com, manasi.d.navare@intel.com
Subject: [PATCH v3 11/13] drm/i915/dg2: use 128b/132b transcoder DDI mode
Date: Thu,  9 Sep 2021 15:52:03 +0300	[thread overview]
Message-ID: <279bfbd979e0256fae13a5231e07e2f4fb665c07.1631191763.git.jani.nikula@intel.com> (raw)
In-Reply-To: <cover.1631191763.git.jani.nikula@intel.com>

128b/132b has a separate transcoder DDI mode, which also requires the
MST transport select to be set. Note that we'll use DP MST also for
single-stream 128b/132b.

Having the FDI and 128b/132b modes share the register mode value
complicates things a bit.

v2:
- Use HAS_DP20 abstraction for 128b/132b mode (Ville)
- Use intel_dp_is_uhbr() helper

Bspec: 50493
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a7b7e4fafcb3..d2b96b2efdfe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -506,7 +506,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 		temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 		temp |= (crtc_state->fdi_lanes - 1) << 1;
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
-		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
+		if (intel_dp_is_uhbr(crtc_state))
+			temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
+		else
+			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
 		if (DISPLAY_VER(dev_priv) >= 12) {
@@ -694,7 +697,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 		break;
 
 	case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
-		ret = type == DRM_MODE_CONNECTOR_VGA;
+		if (HAS_DP20(dev_priv))
+			/* 128b/132b */
+			ret = false;
+		else
+			/* FDI */
+			ret = type == DRM_MODE_CONNECTOR_VGA;
 		break;
 
 	default:
@@ -781,8 +789,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 		if ((tmp & port_mask) != ddi_select)
 			continue;
 
-		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
-		    TRANS_DDI_MODE_SELECT_DP_MST)
+		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
+		    (HAS_DP20(dev_priv) &&
+		     (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
 			mst_pipe_mask |= BIT(p);
 
 		*pipe_mask |= BIT(p);
@@ -3573,9 +3582,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
 		pipe_config->lane_count = 4;
 		break;
-	case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
-		pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
-		break;
 	case TRANS_DDI_MODE_SELECT_DP_SST:
 		if (encoder->type == INTEL_OUTPUT_EDP)
 			pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
@@ -3604,6 +3610,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 			pipe_config->infoframes.enable |=
 				intel_hdmi_infoframes_enabled(encoder, pipe_config);
 		break;
+	case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
+		if (!HAS_DP20(dev_priv)) {
+			/* FDI */
+			pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
+			break;
+		}
+		fallthrough; /* 128b/132b */
 	case TRANS_DDI_MODE_SELECT_DP_MST:
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
 		pipe_config->lane_count =
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,
	ville.syrjala@linux.intel.com, manasi.d.navare@intel.com
Subject: [Intel-gfx] [PATCH v3 11/13] drm/i915/dg2: use 128b/132b transcoder DDI mode
Date: Thu,  9 Sep 2021 15:52:03 +0300	[thread overview]
Message-ID: <279bfbd979e0256fae13a5231e07e2f4fb665c07.1631191763.git.jani.nikula@intel.com> (raw)
In-Reply-To: <cover.1631191763.git.jani.nikula@intel.com>

128b/132b has a separate transcoder DDI mode, which also requires the
MST transport select to be set. Note that we'll use DP MST also for
single-stream 128b/132b.

Having the FDI and 128b/132b modes share the register mode value
complicates things a bit.

v2:
- Use HAS_DP20 abstraction for 128b/132b mode (Ville)
- Use intel_dp_is_uhbr() helper

Bspec: 50493
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a7b7e4fafcb3..d2b96b2efdfe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -506,7 +506,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 		temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 		temp |= (crtc_state->fdi_lanes - 1) << 1;
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
-		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
+		if (intel_dp_is_uhbr(crtc_state))
+			temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
+		else
+			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
 		if (DISPLAY_VER(dev_priv) >= 12) {
@@ -694,7 +697,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 		break;
 
 	case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
-		ret = type == DRM_MODE_CONNECTOR_VGA;
+		if (HAS_DP20(dev_priv))
+			/* 128b/132b */
+			ret = false;
+		else
+			/* FDI */
+			ret = type == DRM_MODE_CONNECTOR_VGA;
 		break;
 
 	default:
@@ -781,8 +789,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 		if ((tmp & port_mask) != ddi_select)
 			continue;
 
-		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
-		    TRANS_DDI_MODE_SELECT_DP_MST)
+		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
+		    (HAS_DP20(dev_priv) &&
+		     (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
 			mst_pipe_mask |= BIT(p);
 
 		*pipe_mask |= BIT(p);
@@ -3573,9 +3582,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
 		pipe_config->lane_count = 4;
 		break;
-	case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
-		pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
-		break;
 	case TRANS_DDI_MODE_SELECT_DP_SST:
 		if (encoder->type == INTEL_OUTPUT_EDP)
 			pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
@@ -3604,6 +3610,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 			pipe_config->infoframes.enable |=
 				intel_hdmi_infoframes_enabled(encoder, pipe_config);
 		break;
+	case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
+		if (!HAS_DP20(dev_priv)) {
+			/* FDI */
+			pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
+			break;
+		}
+		fallthrough; /* 128b/132b */
 	case TRANS_DDI_MODE_SELECT_DP_MST:
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
 		pipe_config->lane_count =
-- 
2.30.2


  parent reply	other threads:[~2021-09-09 12:53 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-09 12:51 [PATCH v3 00/13] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
2021-09-09 12:51 ` [Intel-gfx] " Jani Nikula
2021-09-09 12:51 ` [PATCH v3 01/13] drm/dp: add DP 2.0 UHBR link rate and bw code conversions Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:40   ` Ville Syrjälä
2021-09-17 12:40     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:51 ` [PATCH v3 02/13] drm/dp: use more of the extended receiver cap Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-09 16:18   ` Lyude Paul
2021-09-09 16:18     ` Lyude Paul
2021-09-09 16:18     ` Lyude Paul
2021-09-09 16:18       ` [Intel-gfx] " Lyude Paul
2021-09-09 12:51 ` [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-21 22:58   ` Nathan Chancellor
2021-09-22  0:45     ` Stephen Rothwell
2021-09-22 11:10     ` Jani Nikula
2021-09-22 13:49       ` Alex Deucher
2021-09-22 13:49         ` Alex Deucher
2021-09-22 17:32         ` [PATCH] drm/amd/display: Only define DP 2.0 symbols if not already defined Harry Wentland
2021-09-22 17:32           ` [Intel-gfx] " Harry Wentland
2021-09-09 12:51 ` [PATCH v3 04/13] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-09 12:51 ` [PATCH v3 05/13] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:54   ` Ville Syrjälä
2021-09-17 12:54     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:51 ` [PATCH v3 06/13] drm/i915/dp: add helper for checking for UHBR link rate Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:41   ` Ville Syrjälä
2021-09-17 12:41     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:51 ` [PATCH v3 07/13] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-09 12:52 ` [PATCH v3 08/13] drm/i915/dp: select 128b/132b channel encoding for UHBR rates Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-09 12:52 ` [PATCH v3 09/13] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-09 12:52 ` [PATCH v3 10/13] drm/i915/dp: add HAS_DP20 macro Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:42   ` Ville Syrjälä
2021-09-17 12:42     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:52 ` Jani Nikula [this message]
2021-09-09 12:52   ` [Intel-gfx] [PATCH v3 11/13] drm/i915/dg2: use 128b/132b transcoder DDI mode Jani Nikula
2021-09-17 12:51   ` Ville Syrjälä
2021-09-17 12:51     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:52 ` [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:53   ` [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} " Ville Syrjälä
2021-09-17 12:53     ` [Intel-gfx] [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} " Ville Syrjälä
2021-09-21  8:44     ` Jani Nikula
2021-09-21  8:44       ` [Intel-gfx] " Jani Nikula
2021-09-09 12:52 ` [PATCH v3 13/13] drm/i915/dg2: update link training " Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-09 13:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work (rev3) Patchwork
2021-09-09 13:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-09 14:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-09 16:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-17 12:54 ` [PATCH v3 00/13] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
2021-09-17 12:54   ` [Intel-gfx] " Jani Nikula
2021-09-17 16:56   ` Maxime Ripard
2021-09-17 16:56     ` [Intel-gfx] " Maxime Ripard
2021-09-21  8:44     ` Jani Nikula
2021-09-21  8:44       ` [Intel-gfx] " Jani Nikula
2021-09-22 12:54 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: dp 2.0 enabling prep work (rev4) Patchwork
2021-09-22 18:24 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: dp 2.0 enabling prep work (rev5) Patchwork

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