From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Thu, 3 May 2018 10:38:54 +0200 Subject: [U-Boot] [PATCH v2 1/7] i.MX6: board: Add BTicino i.MX6DL Mamoj initial support In-Reply-To: References: <20180411123615.15130-1-jagan@amarulasolutions.com> <20180411123615.15130-2-jagan@amarulasolutions.com> <85cf1d0c-5e33-18ea-07bb-1f033d1e281e@denx.de> <6128a15e-384c-04e9-44ab-e062adb8e502@denx.de> Message-ID: <27f23c98-c407-4429-e5ea-72ead80782dd@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 02/05/2018 14:41, Jagan Teki wrote: > Hi Stefano, > > On Thu, Apr 26, 2018 at 1:16 PM, Stefano Babic wrote: >> On 26/04/2018 09:33, Jagan Teki wrote: >>> On Thu, Apr 26, 2018 at 12:47 PM, Stefano Babic wrote: >>>> Hi Jagan, >>>> > > [snip] > >>>>> + >>>>> +static int mx6dl_dcd_table[] = { >>>>> + 0x020e0774, 0x000C0000, /* MX6_IOM_GRP_DDR_TYPE */ >>>>> + 0x020e0754, 0x00000000, /* MX6_IOM_GRP_DDRPKE */ >>>>> + >>>>> + 0x020e04ac, 0x00000028, /* MX6_IOM_DRAM_SDCLK_0 */ >>>>> + 0x020e04b0, 0x00000028, /* MX6_IOM_DRAM_SDCLK_1 */ >>>>> + >>>>> + 0x020e0464, 0x00000028, /* MX6_IOM_DRAM_CAS */ >>>>> + 0x020e0490, 0x00000028, /* MX6_IOM_DRAM_RAS */ >>>>> + 0x020e074c, 0x00000028, /* MX6_IOM_GRP_ADDDS */ >>>>> + >>>>> + 0x020e0494, 0x00000028, /* MX6_IOM_DRAM_RESET */ >>>>> + 0x020e04a0, 0x00000000, /* MX6_IOM_DRAM_SDBA2 */ >>>>> + 0x020e04b4, 0x00000028, /* MX6_IOM_DRAM_SDODT0 */ >>>>> + 0x020e04b8, 0x00000028, /* MX6_IOM_DRAM_SDODT1 */ >>>>> + 0x020e076c, 0x00000028, /* MX6_IOM_GRP_CTLDS */ >>>>> + >>>>> + 0x020e0750, 0x00020000, /* MX6_IOM_GRP_DDRMODE_CTL */ >>>>> + 0x020e04bc, 0x00000028, /* MX6_IOM_DRAM_SDQS0 */ >>>>> + 0x020e04c0, 0x00000028, /* MX6_IOM_DRAM_SDQS1 */ >>>>> + 0x020e04c4, 0x00000028, /* MX6_IOM_DRAM_SDQS2 */ >>>>> + 0x020e04c8, 0x00000028, /* MX6_IOM_DRAM_SDQS3 */ >>>>> + >>>>> + 0x020e0760, 0x00020000, /* MX6_IOM_GRP_DDRMODE */ >>>>> + 0x020e0764, 0x00000028, /* MX6_IOM_GRP_B0DS */ >>>>> + 0x020e0770, 0x00000028, /* MX6_IOM_GRP_B1DS */ >>>>> + 0x020e0778, 0x00000028, /* MX6_IOM_GRP_B2DS */ >>>>> + 0x020e077c, 0x00000028, /* MX6_IOM_GRP_B3DS */ >>>>> + >>>>> + 0x020e0470, 0x00000028, /* MX6_IOM_DRAM_DQM0 */ >>>>> + 0x020e0474, 0x00000028, /* MX6_IOM_DRAM_DQM1 */ >>>>> + 0x020e0478, 0x00000028, /* MX6_IOM_DRAM_DQM2 */ >>>>> + 0x020e047c, 0x00000028, /* MX6_IOM_DRAM_DQM3 */ >>>>> + >>>>> + 0x021b001c, 0x00008000, /* MMDC0_MDSCR */ >>>>> + >>>>> + 0x021b0800, 0xA1390003, /* DDR_PHY_P0_MPZQHWCTRL */ >>>>> + >>>>> + 0x021b080c, 0x0042004b, /* MMDC1_MPWLDECTRL0 */ >>>>> + 0x021b0810, 0x0038003c, /* MMDC1_MPWLDECTRL1 */ >>>>> + >>>>> + 0x021b083c, 0x42340230, /* MPDGCTRL0 PHY0 */ >>>>> + 0x021b0840, 0x0228022c, /* MPDGCTRL1 PHY0 */ >>>>> + >>>>> + 0x021b0848, 0x42444646, /* MPRDDLCTL PHY0 */ >>>>> + >>>>> + 0x021b0850, 0x38382e2e, /* MPWRDLCTL PHY0 */ >>>>> + >>>>> + 0x021b081c, 0x33333333, /* DDR_PHY_P0_MPREDQBY0DL3 */ >>>>> + 0x021b0820, 0x33333333, /* DDR_PHY_P0_MPREDQBY1DL3 */ >>>>> + 0x021b0824, 0x33333333, /* DDR_PHY_P0_MPREDQBY2DL3 */ >>>>> + 0x021b0828, 0x33333333, /* DDR_PHY_P0_MPREDQBY3DL3 */ >>>>> + >>>>> + 0x021b08b8, 0x00000800, /* DDR_PHY_P0_MPMUR0 */ >>>>> + >>>>> + 0x021b0004, 0x0002002D, /* MMDC0_MDPDC */ >>>>> + 0x021b0008, 0x00333040, /* MMDC0_MDOTC */ >>>>> + 0x021b000c, 0x3F4352F3, /* MMDC0_MDCFG0 */ >>>>> + 0x021b0010, 0xB66D8B63, /* MMDC0_MDCFG1 */ >>>>> + 0x021b0014, 0x01FF00DB, /* MMDC0_MDCFG2 */ >>>>> + >>>>> + 0x021b0018, 0x00011740, /* MMDC0_MDMISC */ >>>>> + 0x021b001c, 0x00008000, /* MMDC0_MDSCR */ >>>>> + 0x021b002c, 0x000026D2, /* MMDC0_MDRWD */ >>>>> + 0x021b0030, 0x00431023, /* MMDC0_MDOR */ >>>>> + 0x021b0040, 0x00000017, /* Chan0 CS0_END */ >>>>> + 0x021b0000, 0x83190000, /* MMDC0_MDCTL */ >>>>> + >>>>> + 0x021b001c, 0x02008032, /* MMDC0_MDSCR MR2 write, CS0 */ >>>>> + 0x021b001c, 0x00008033, /* MMDC0_MDSCR, MR3 write, CS0 */ >>>>> + 0x021b001c, 0x00048031, /* MMDC0_MDSCR, MR1 write, CS0 */ >>>>> + 0x021b001c, 0x15208030, /* MMDC0_MDSCR, MR0write, CS0 */ >>>>> + 0x021b001c, 0x04008040, /* MMDC0_MDSCR */ >>>>> + >>>>> + 0x021b0020, 0x00007800, /* MMDC0_MDREF */ >>>>> + >>>>> + 0x021b0818, 0x00022227, /* DDR_PHY_P0_MPODTCTRL */ >>>>> + >>>>> + 0x021b0004, 0x0002556D, /* MMDC0_MDPDC */ >>>>> + 0x021b0404, 0x00011006, /* MMDC0_MAPSR ADOPT */ >>>>> + 0x021b001c, 0x00000000, /* MMDC0_MDSCR */ >>>>> +}; >>>>> + >>>> >>>> Sorry to have not raised this before. I saw this the first time, but I >>>> did not understand. I tried to find a reason for it, but still I had no >>>> answer. >>>> >>>> This is a DL, and DDR support is full integrated in U-Boot, including >>>> dynamic calibration if desired. What is the reason to dump the DCD table >>>> into code and push it with ddr_init, instead of setting structures for >>>> chip, gpr and calibration as most of boards are doing ? If you dump the >>>> table, you could this in the .cfg file where the DCD table belongs to, >>>> of course adding entries for DDR initialisation. I do not see after long >>>> thoughts any reason to go in this way. >>> >>> Like initializing ddr config and calibration using mx6sdl_dram_iocfg >>> and mx6_dram_cfg? yes I usually does the same instead of hot codding >>> hex values. >> >> Yes, this is what I mean. > > ddr calibration here has reinitialized few of same registers multiple > times with a sequence, using mx6_dram_cfg I can't achieve the same. Do you mean dynamic calibration CONFIG_MX6_DDRCAL ? If this is the case, you can still use the static values passing the parameters you got from ddr_stress. > I > need to dig further on to this for proper working register values > meanwhile can it be possible to apply this sequence as of now? I do not think this is a good idea - I really prefer to get in the final solution. Thanks, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================