From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Wed, 13 Feb 2019 13:00:04 +0100 Subject: [U-Boot] [PATCH v7 3/7] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading In-Reply-To: <1550046120.10013.3.camel@intel.com> References: <1548946304-17460-1-git-send-email-tien.fong.chee@intel.com> <1548946304-17460-4-git-send-email-tien.fong.chee@intel.com> <8b209627-cd11-8343-2d26-5716a5fca374@denx.de> <1548993853.11133.21.camel@intel.com> <76aa99ad-8f89-1ddc-9686-733a5362509d@denx.de> <1550046120.10013.3.camel@intel.com> Message-ID: <283635ef-3b68-ce68-8e8e-375add4b472a@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On 2/13/19 9:22 AM, Chee, Tien Fong wrote: > On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote: >> On 2/1/19 5:04 AM, Chee, Tien Fong wrote: >>> >>> On Thu, 2019-01-31 at 15:55 +0100, Marek Vasut wrote: >>>> >>>> On 1/31/19 3:51 PM, tien.fong.chee at intel.com wrote: >>>>> >>>>> >>>>> From: Tien Fong Chee >>>>> >>>>> Add FPGA driver to support program FPGA with FPGA bitstream >>>>> loading >>>>> from >>>>> filesystem. The driver are designed based on generic firmware >>>>> loader >>>>> framework. The driver can handle FPGA program operation from >>>>> loading FPGA >>>>> bitstream in flash to memory and then to program FPGA. >>>>> >>>>> Signed-off-by: Tien Fong Chee >>>>> >>>>> --- >>>>> >>>>> changes for v7 >>>>> - Restructure the FPGA driver to support both peripheral >>>>> bitstream >>>>> and core >>>>>   bitstream bundled into FIT image. >>>>> - Support loadable property for core bitstream. User can set >>>>> loadable >>>>>   in DDR for better performance. This loading would be done in >>>>> one >>>>> large >>>>>   chunk instead of chunk by chunk loading with small memory >>>>> buffer. >>>>> --- >>>>>  arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts       |  18 + >>>>>  .../include/mach/fpga_manager_arria10.h            |  39 +- >>>>>  drivers/fpga/socfpga_arria10.c                     | 417 >>>>> ++++++++++++++++++++- >>>>>  3 files changed, 457 insertions(+), 17 deletions(-) >>>>> >>>>> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts >>>>> b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts >>>>> index 998d811..dc55618 100644 >>>>> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts >>>>> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts >>>>> @@ -18,6 +18,24 @@ >>>>>  /dts-v1/; >>>>>  #include "socfpga_arria10_socdk.dtsi" >>>>>   >>>>> +/ { >>>>> + chosen { >>>>> + firmware-loader = &fs_loader0; >>>> Shouldn't this be <&fs_loader0>; ? >>>> How did this even pass the DTC ? >>> So <> is compulsory required for phandle? No error complaint from >>> DTC. >> Yes > I just checked the codes, this &fs_loader0 without <> is valid, because > this is not a phandle, instead it is a label which will be expanded to > the node's full path. Shouldn't it be a phandle ? -- Best regards, Marek Vasut