From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22198C433FE for ; Wed, 2 Mar 2022 23:48:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229519AbiCBXtA (ORCPT ); Wed, 2 Mar 2022 18:49:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229472AbiCBXs6 (ORCPT ); Wed, 2 Mar 2022 18:48:58 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3C1C12D0BF; Wed, 2 Mar 2022 15:48:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646264887; x=1677800887; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=ePGEAQEiXFqvztXXwX7CVXcMlSsk/5spLo6n3yeErdw=; b=hP/KNV86MKsclgD+4MtwOCEE2O70j6Ga/sdjWnRbsH9Byq9GfWr6NHwc p0ywp4kh033g/6L3xd+pb+6IqYDkpUPUI6GDWbhpNHxdLGhlJPVcmFPMz /C4S868Gf4S41mJYFqrXXpM8VPVPn9RL2SEdc9CASJSE5Z00TXgopIKF/ c=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 02 Mar 2022 15:48:06 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2022 15:48:05 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Wed, 2 Mar 2022 15:48:05 -0800 Received: from [10.110.107.103] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Wed, 2 Mar 2022 15:48:04 -0800 Message-ID: <283d65cc-5785-4d17-f998-44a6bf8e1c3d@quicinc.com> Date: Wed, 2 Mar 2022 15:48:04 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [PATCH v2 2/6] arm64: dts: qcom: sdm630: Drop flags for mdss irqs Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Rob Herring CC: Stephen Boyd , , , References: <20220302225411.2456001-1-dmitry.baryshkov@linaro.org> <20220302225411.2456001-2-dmitry.baryshkov@linaro.org> From: Abhinav Kumar In-Reply-To: <20220302225411.2456001-2-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 3/2/2022 2:54 PM, Dmitry Baryshkov wrote: > The number of interrupt cells for the mdss interrupt controller is 1, > meaning there should only be one cell for the interrupt number, not two. > Drop the second cell containing (unused) irq flags. > > Reviewed-by: Stephen Boyd > Fixes: b52555d590d1 ("arm64: dts: qcom: sdm630: Add MDSS nodes") > Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar > --- > arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi > index 240293592ef9..7f875bf9390a 100644 > --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi > @@ -1453,7 +1453,7 @@ mdp: mdp@c901000 { > reg-names = "mdp_phys"; > > interrupt-parent = <&mdss>; > - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <0>; > > assigned-clocks = <&mmcc MDSS_MDP_CLK>, > <&mmcc MDSS_VSYNC_CLK>; > @@ -1530,7 +1530,7 @@ dsi0: dsi@c994000 { > power-domains = <&rpmpd SDM660_VDDCX>; > > interrupt-parent = <&mdss>; > - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <4>; > > assigned-clocks = <&mmcc BYTE0_CLK_SRC>, > <&mmcc PCLK0_CLK_SRC>;