* [PATCH v5 00/10] GICv3 LPI and ITS feature implementation
@ 2021-06-30 15:31 Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework Shashi Mallela
` (10 more replies)
0 siblings, 11 replies; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
This patchset implements qemu device model for enabling physical
LPI support and ITS functionality in GIC as per GICv3 specification.
Both flat table and 2 level tables are implemented.The ITS commands
for adding/deleting ITS table entries,trigerring LPI interrupts are
implemented.Translated LPI interrupt ids are processed by redistributor
to determine priority and set pending state appropriately before
forwarding the same to cpu interface.
The ITS feature support has been added to sbsa-ref platform as well as
virt platform,wherein the emulated functionality co-exists with kvm
kernel functionality.
Changes in v5:
- v4 review comments addressed
- All kvm_unit_tests PASS
Shashi Mallela (10):
hw/intc: GICv3 ITS initial framework
hw/intc: GICv3 ITS register definitions added
hw/intc: GICv3 ITS command queue framework
hw/intc: GICv3 ITS Command processing
hw/intc: GICv3 ITS Feature enablement
hw/intc: GICv3 redistributor ITS processing
hw/arm/sbsa-ref: add ITS support in SBSA GIC
tests/data/acpi/virt: Add IORT files for ITS
hw/arm/virt: add ITS support in virt GIC
tests/data/acpi/virt: Update IORT files for ITS
hw/arm/sbsa-ref.c | 26 +-
hw/arm/virt.c | 28 +-
hw/intc/arm_gicv3.c | 14 +
hw/intc/arm_gicv3_common.c | 13 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_dist.c | 5 +-
hw/intc/arm_gicv3_its.c | 1296 ++++++++++++++++++++++++
hw/intc/arm_gicv3_its_common.c | 7 +-
hw/intc/arm_gicv3_its_kvm.c | 2 +-
hw/intc/arm_gicv3_redist.c | 154 ++-
hw/intc/gicv3_internal.h | 187 +++-
hw/intc/meson.build | 1 +
include/hw/arm/virt.h | 2 +
include/hw/intc/arm_gicv3_common.h | 13 +
include/hw/intc/arm_gicv3_its_common.h | 32 +-
target/arm/kvm_arm.h | 4 +-
tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes
20 files changed, 1764 insertions(+), 27 deletions(-)
create mode 100644 hw/intc/arm_gicv3_its.c
create mode 100644 tests/data/acpi/virt/IORT
create mode 100644 tests/data/acpi/virt/IORT.memhp
create mode 100644 tests/data/acpi/virt/IORT.numamem
create mode 100644 tests/data/acpi/virt/IORT.pxb
--
2.27.0
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-07-05 14:58 ` Peter Maydell
2021-07-06 7:44 ` Eric Auger
2021-06-30 15:31 ` [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added Shashi Mallela
` (9 subsequent siblings)
10 siblings, 2 replies; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_its.c | 240 +++++++++++++++++++++++++
hw/intc/arm_gicv3_its_common.c | 7 +-
hw/intc/arm_gicv3_its_kvm.c | 2 +-
hw/intc/gicv3_internal.h | 88 +++++++--
hw/intc/meson.build | 1 +
include/hw/intc/arm_gicv3_its_common.h | 9 +-
6 files changed, 331 insertions(+), 16 deletions(-)
create mode 100644 hw/intc/arm_gicv3_its.c
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
new file mode 100644
index 0000000000..545cda3665
--- /dev/null
+++ b/hw/intc/arm_gicv3_its.c
@@ -0,0 +1,240 @@
+/*
+ * ITS emulation for a GICv3-based system
+ *
+ * Copyright Linaro.org 2021
+ *
+ * Authors:
+ * Shashi Mallela <shashi.mallela@linaro.org>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
+ * option) any later version. See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "gicv3_internal.h"
+#include "qom/object.h"
+
+typedef struct GICv3ITSClass GICv3ITSClass;
+/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
+DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
+ ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
+
+struct GICv3ITSClass {
+ GICv3ITSCommonClass parent_class;
+ void (*parent_reset)(DeviceState *dev);
+};
+
+static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
+ uint64_t data, unsigned size,
+ MemTxAttrs attrs)
+{
+ MemTxResult result = MEMTX_OK;
+
+ return result;
+}
+
+static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+ MemTxResult result = MEMTX_OK;
+
+ return result;
+}
+
+static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+ MemTxResult result = MEMTX_OK;
+
+ return result;
+}
+
+static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+ MemTxResult result = MEMTX_OK;
+
+ return result;
+}
+
+static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+ MemTxResult result = MEMTX_OK;
+
+ return result;
+}
+
+static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
+ MemTxResult result;
+
+ switch (size) {
+ case 4:
+ result = its_readl(s, offset, data, attrs);
+ break;
+ case 8:
+ result = its_readll(s, offset, data, attrs);
+ break;
+ default:
+ result = MEMTX_ERROR;
+ break;
+ }
+
+ if (result == MEMTX_ERROR) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest read at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+ /*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+ result = MEMTX_OK;
+ *data = 0;
+ }
+ return result;
+}
+
+static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size, MemTxAttrs attrs)
+{
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
+ MemTxResult result;
+
+ switch (size) {
+ case 4:
+ result = its_writel(s, offset, data, attrs);
+ break;
+ case 8:
+ result = its_writell(s, offset, data, attrs);
+ break;
+ default:
+ result = MEMTX_ERROR;
+ break;
+ }
+
+ if (result == MEMTX_ERROR) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+ /*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+ result = MEMTX_OK;
+ }
+ return result;
+}
+
+static const MemoryRegionOps gicv3_its_control_ops = {
+ .read_with_attrs = gicv3_its_read,
+ .write_with_attrs = gicv3_its_write,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const MemoryRegionOps gicv3_its_translation_ops = {
+ .write_with_attrs = gicv3_its_translation_write,
+ .valid.min_access_size = 2,
+ .valid.max_access_size = 4,
+ .impl.min_access_size = 2,
+ .impl.max_access_size = 4,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
+{
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
+
+ gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops);
+
+ if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
+ /* set the ITS default features supported */
+ s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
+ GITS_TYPE_PHYSICAL);
+ s->typer = FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE,
+ ITS_ITT_ENTRY_SIZE - 1);
+ s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS, ITS_IDBITS);
+ s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS, ITS_DEVBITS);
+ s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1);
+ s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS, ITS_CIDBITS);
+ }
+}
+
+static void gicv3_its_reset(DeviceState *dev)
+{
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
+ GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
+
+ if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
+ c->parent_reset(dev);
+
+ /* Quiescent bit reset to 1 */
+ s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
+
+ /*
+ * setting GITS_BASER0.Type = 0b001 (Device)
+ * GITS_BASER1.Type = 0b100 (Collection Table)
+ * GITS_BASER<n>.Type,where n = 3 to 7 are 0b00 (Unimplemented)
+ * GITS_BASER<0,1>.Page_Size = 64KB
+ * and default translation table entry size to 16 bytes
+ */
+ s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE,
+ GITS_ITT_TYPE_DEVICE);
+ s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, PAGESIZE,
+ GITS_BASER_PAGESIZE_64K);
+ s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, ENTRYSIZE,
+ GITS_DTE_SIZE - 1);
+
+ s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE,
+ GITS_ITT_TYPE_COLLECTION);
+ s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, PAGESIZE,
+ GITS_BASER_PAGESIZE_64K);
+ s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE,
+ GITS_CTE_SIZE - 1);
+ }
+}
+
+static Property gicv3_its_props[] = {
+ DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3",
+ GICv3State *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void gicv3_its_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
+
+ dc->realize = gicv3_arm_its_realize;
+ device_class_set_props(dc, gicv3_its_props);
+ device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
+}
+
+static const TypeInfo gicv3_its_info = {
+ .name = TYPE_ARM_GICV3_ITS,
+ .parent = TYPE_ARM_GICV3_ITS_COMMON,
+ .instance_size = sizeof(GICv3ITSState),
+ .class_init = gicv3_its_class_init,
+ .class_size = sizeof(GICv3ITSClass),
+};
+
+static void gicv3_its_register_types(void)
+{
+ type_register_static(&gicv3_its_info);
+}
+
+type_init(gicv3_its_register_types)
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
index 66c4c6a188..7d7f3882e7 100644
--- a/hw/intc/arm_gicv3_its_common.c
+++ b/hw/intc/arm_gicv3_its_common.c
@@ -50,6 +50,8 @@ static int gicv3_its_post_load(void *opaque, int version_id)
static const VMStateDescription vmstate_its = {
.name = "arm_gicv3_its",
+ .version_id = 1,
+ .minimum_version_id = 1,
.pre_save = gicv3_its_pre_save,
.post_load = gicv3_its_post_load,
.priority = MIG_PRI_GICV3_ITS,
@@ -99,14 +101,15 @@ static const MemoryRegionOps gicv3_its_trans_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
+void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
+ const MemoryRegionOps *tops)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
"control", ITS_CONTROL_SIZE);
memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
- &gicv3_its_trans_ops, s,
+ tops ? tops : &gicv3_its_trans_ops, s,
"translation", ITS_TRANS_SIZE);
/* Our two regions are always adjacent, therefore we now combine them
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
index b554d2ede0..0b4cbed28b 100644
--- a/hw/intc/arm_gicv3_its_kvm.c
+++ b/hw/intc/arm_gicv3_its_kvm.c
@@ -106,7 +106,7 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0);
- gicv3_its_init_mmio(s, NULL);
+ gicv3_its_init_mmio(s, NULL, NULL);
if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
GITS_CTLR)) {
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 05303a55c8..e0b06930a7 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -24,6 +24,7 @@
#ifndef QEMU_ARM_GICV3_INTERNAL_H
#define QEMU_ARM_GICV3_INTERNAL_H
+#include "hw/registerfields.h"
#include "hw/intc/arm_gicv3_common.h"
/* Distributor registers, as offsets from the distributor base address */
@@ -67,6 +68,9 @@
#define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_RWP (1U << 31)
+/* 16 bits EventId */
+#define GICD_TYPER_IDBITS 0xf
+
/*
* Redistributor frame offsets from RD_base
*/
@@ -122,18 +126,6 @@
#define GICR_WAKER_ProcessorSleep (1U << 1)
#define GICR_WAKER_ChildrenAsleep (1U << 2)
-#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
-#define GICR_PROPBASER_ADDR_MASK (0xfffffffffULL << 12)
-#define GICR_PROPBASER_SHAREABILITY_MASK (3U << 10)
-#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
-#define GICR_PROPBASER_IDBITS_MASK (0x1f)
-
-#define GICR_PENDBASER_PTZ (1ULL << 62)
-#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
-#define GICR_PENDBASER_ADDR_MASK (0xffffffffULL << 16)
-#define GICR_PENDBASER_SHAREABILITY_MASK (3U << 10)
-#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
-
#define ICC_CTLR_EL1_CBPR (1U << 0)
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
#define ICC_CTLR_EL1_PMHE (1U << 6)
@@ -239,6 +231,78 @@
#define ICH_VTR_EL2_PREBITS_SHIFT 26
#define ICH_VTR_EL2_PRIBITS_SHIFT 29
+/* ITS Registers */
+
+FIELD(GITS_BASER, SIZE, 0, 8)
+FIELD(GITS_BASER, PAGESIZE, 8, 2)
+FIELD(GITS_BASER, SHAREABILITY, 10, 2)
+FIELD(GITS_BASER, PHYADDR, 12, 36)
+FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
+FIELD(GITS_BASER, PHYADDRH_64K, 48, 4)
+FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
+FIELD(GITS_BASER, OUTERCACHE, 53, 3)
+FIELD(GITS_BASER, TYPE, 56, 3)
+FIELD(GITS_BASER, INNERCACHE, 59, 3)
+FIELD(GITS_BASER, INDIRECT, 62, 1)
+FIELD(GITS_BASER, VALID, 63, 1)
+
+FIELD(GITS_CTLR, QUIESCENT, 31, 1)
+
+FIELD(GITS_TYPER, PHYSICAL, 0, 1)
+FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4)
+FIELD(GITS_TYPER, IDBITS, 8, 5)
+FIELD(GITS_TYPER, DEVBITS, 13, 5)
+FIELD(GITS_TYPER, SEIS, 18, 1)
+FIELD(GITS_TYPER, PTA, 19, 1)
+FIELD(GITS_TYPER, CIDBITS, 32, 4)
+FIELD(GITS_TYPER, CIL, 36, 1)
+
+#define GITS_BASER_PAGESIZE_4K 0
+#define GITS_BASER_PAGESIZE_16K 1
+#define GITS_BASER_PAGESIZE_64K 2
+
+#define GITS_ITT_TYPE_DEVICE 1ULL
+#define GITS_ITT_TYPE_COLLECTION 4ULL
+
+/**
+ * Default features advertised by this version of ITS
+ */
+/* Physical LPIs supported */
+#define GITS_TYPE_PHYSICAL (1U << 0)
+
+/*
+ * 12 bytes Interrupt translation Table Entry size
+ * ITE Lower 8 Bytes
+ * Valid = 1 bit,InterruptType = 1 bit,
+ * Size of LPI number space[considering max 24 bits],
+ * Size of LPI number space[considering max 24 bits],
+ * ITE Higher 4 Bytes
+ * ICID = 16 bits,
+ * vPEID = 16 bits
+ */
+#define ITS_ITT_ENTRY_SIZE 0xC
+
+/* 16 bits EventId */
+#define ITS_IDBITS GICD_TYPER_IDBITS
+
+/* 16 bits DeviceId */
+#define ITS_DEVBITS 0xF
+
+/* 16 bits CollectionId */
+#define ITS_CIDBITS 0xF
+
+/*
+ * 8 bytes Device Table Entry size
+ * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits
+ */
+#define GITS_DTE_SIZE (0x8ULL)
+
+/*
+ * 8 bytes Collection Table Entry size
+ * Valid = 1 bit,RDBase = 36 bits(considering max RDBASE)
+ */
+#define GITS_CTE_SIZE (0x8ULL)
+
/* Special interrupt IDs */
#define INTID_SECURE 1020
#define INTID_NONSECURE 1021
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 6e52a166e3..4dcfea6aa8 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -8,6 +8,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
'arm_gicv3_dist.c',
'arm_gicv3_its_common.c',
'arm_gicv3_redist.c',
+ 'arm_gicv3_its.c',
))
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c'))
diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
index 5a0952b404..65d1191db1 100644
--- a/include/hw/intc/arm_gicv3_its_common.h
+++ b/include/hw/intc/arm_gicv3_its_common.h
@@ -25,17 +25,22 @@
#include "hw/intc/arm_gicv3_common.h"
#include "qom/object.h"
+#define TYPE_ARM_GICV3_ITS "arm-gicv3-its"
+
#define ITS_CONTROL_SIZE 0x10000
#define ITS_TRANS_SIZE 0x10000
#define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
#define GITS_CTLR 0x0
#define GITS_IIDR 0x4
+#define GITS_TYPER 0x8
#define GITS_CBASER 0x80
#define GITS_CWRITER 0x88
#define GITS_CREADR 0x90
#define GITS_BASER 0x100
+#define GITS_TRANSLATER 0x0040
+
struct GICv3ITSState {
SysBusDevice parent_obj;
@@ -52,6 +57,7 @@ struct GICv3ITSState {
/* Registers */
uint32_t ctlr;
uint32_t iidr;
+ uint64_t typer;
uint64_t cbaser;
uint64_t cwriter;
uint64_t creadr;
@@ -62,7 +68,8 @@ struct GICv3ITSState {
typedef struct GICv3ITSState GICv3ITSState;
-void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
+void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
+ const MemoryRegionOps *tops);
#define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-07-06 9:29 ` Eric Auger
2021-06-30 15:31 ` [PATCH v5 03/10] hw/intc: GICv3 ITS command queue framework Shashi Mallela
` (8 subsequent siblings)
10 siblings, 1 reply; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_its.c | 376 +++++++++++++++++++++++++
hw/intc/gicv3_internal.h | 31 +-
include/hw/intc/arm_gicv3_common.h | 3 +
include/hw/intc/arm_gicv3_its_common.h | 23 ++
4 files changed, 432 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 545cda3665..2d786a1e21 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -28,6 +28,160 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
+{
+ uint64_t result = 0;
+
+ switch (page_sz) {
+ case GITS_PAGE_SIZE_4K:
+ case GITS_PAGE_SIZE_16K:
+ result = FIELD_EX64(value, GITS_BASER, PHYADDR);
+ break;
+
+ case GITS_PAGE_SIZE_64K:
+ result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16;
+ result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48;
+ break;
+
+ default:
+ break;
+ }
+ return result;
+}
+
+/*
+ * This function extracts the ITS Device and Collection table specific
+ * parameters (like base_addr, size etc) from GITS_BASER register.
+ * It is called during ITS enable and also during post_load migration
+ */
+static void extract_table_params(GICv3ITSState *s)
+{
+ uint16_t num_pages = 0;
+ uint8_t page_sz_type;
+ uint8_t type;
+ uint32_t page_sz = 0;
+ uint64_t value;
+
+ for (int i = 0; i < 8; i++) {
+ value = s->baser[i];
+
+ if (!value) {
+ continue;
+ }
+
+ page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
+
+ switch (page_sz_type) {
+ case 0:
+ page_sz = GITS_PAGE_SIZE_4K;
+ break;
+
+ case 1:
+ page_sz = GITS_PAGE_SIZE_16K;
+ break;
+
+ case 2:
+ case 3:
+ page_sz = GITS_PAGE_SIZE_64K;
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
+
+ type = FIELD_EX64(value, GITS_BASER, TYPE);
+
+ switch (type) {
+
+ case GITS_ITT_TYPE_DEVICE:
+ memset(&s->dt, 0 , sizeof(s->dt));
+ s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+ if (!s->dt.valid) {
+ return;
+ }
+
+ s->dt.page_sz = page_sz;
+ s->dt.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+ s->dt.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+ if (!s->dt.indirect) {
+ s->dt.max_entries = (num_pages * page_sz) / s->dt.entry_sz;
+ } else {
+ s->dt.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->dt.entry_sz));
+ }
+
+ s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s->typer, GITS_TYPER,
+ DEVBITS) + 1));
+
+ s->dt.base_addr = baser_base_addr(value, page_sz);
+
+ break;
+
+ case GITS_ITT_TYPE_COLLECTION:
+ memset(&s->ct, 0 , sizeof(s->ct));
+ s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+ /*
+ * GITS_TYPER.HCC is 0 for this implementation
+ * hence writes are discarded if ct.valid is 0
+ */
+ if (!s->ct.valid) {
+ return;
+ }
+
+ s->ct.page_sz = page_sz;
+ s->ct.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+ s->ct.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+ if (!s->ct.indirect) {
+ s->ct.max_entries = (num_pages * page_sz) / s->ct.entry_sz;
+ } else {
+ s->ct.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->ct.entry_sz));
+ }
+
+ if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
+ s->ct.maxids.max_collids = (1UL << (FIELD_EX64(s->typer,
+ GITS_TYPER, CIDBITS) + 1));
+ } else {
+ /* 16-bit CollectionId supported when CIL == 0 */
+ s->ct.maxids.max_collids = (1UL << 16);
+ }
+
+ s->ct.base_addr = baser_base_addr(value, page_sz);
+
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+static void extract_cmdq_params(GICv3ITSState *s)
+{
+ uint16_t num_pages = 0;
+ uint64_t value = s->cbaser;
+
+ num_pages = FIELD_EX64(value, GITS_CBASER, SIZE) + 1;
+
+ memset(&s->cq, 0 , sizeof(s->cq));
+ s->cq.valid = FIELD_EX64(value, GITS_CBASER, VALID);
+
+ if (s->cq.valid) {
+ s->cq.max_entries = (num_pages * GITS_PAGE_SIZE_4K) /
+ GITS_CMDQ_ENTRY_SIZE;
+ s->cq.base_addr = FIELD_EX64(value, GITS_CBASER, PHYADDR);
+ s->cq.base_addr <<= R_GITS_CBASER_PHYADDR_SHIFT;
+ }
+}
+
static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
uint64_t data, unsigned size,
MemTxAttrs attrs)
@@ -41,7 +195,99 @@ static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
uint64_t value, MemTxAttrs attrs)
{
MemTxResult result = MEMTX_OK;
+ int index;
+ switch (offset) {
+ case GITS_CTLR:
+ s->ctlr |= (value & ~(s->ctlr));
+
+ if (s->ctlr & ITS_CTLR_ENABLED) {
+ extract_table_params(s);
+ extract_cmdq_params(s);
+ s->creadr = 0;
+ }
+ break;
+ case GITS_CBASER:
+ /*
+ * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
+ * already enabled
+ */
+ if (!(s->ctlr & ITS_CTLR_ENABLED)) {
+ s->cbaser = deposit64(s->cbaser, 0, 32, value);
+ s->creadr = 0;
+ s->cwriter = s->creadr;
+ }
+ break;
+ case GITS_CBASER + 4:
+ /*
+ * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
+ * already enabled
+ */
+ if (!(s->ctlr & ITS_CTLR_ENABLED)) {
+ s->cbaser = deposit64(s->cbaser, 32, 32, value);
+ s->creadr = 0;
+ s->cwriter = s->creadr;
+ }
+ break;
+ case GITS_CWRITER:
+ s->cwriter = deposit64(s->cwriter, 0, 32,
+ (value & ~R_GITS_CWRITER_RETRY_MASK));
+ break;
+ case GITS_CWRITER + 4:
+ s->cwriter = deposit64(s->cwriter, 32, 32, value);
+ break;
+ case GITS_CREADR:
+ if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
+ s->creadr = deposit64(s->creadr, 0, 32,
+ (value & ~R_GITS_CREADR_STALLED_MASK));
+ } else {
+ /* RO register, ignore the write */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write to RO register at offset "
+ TARGET_FMT_plx "\n", __func__, offset);
+ }
+ break;
+ case GITS_CREADR + 4:
+ if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
+ s->creadr = deposit64(s->creadr, 32, 32, value);
+ } else {
+ /* RO register, ignore the write */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write to RO register at offset "
+ TARGET_FMT_plx "\n", __func__, offset);
+ }
+ break;
+ case GITS_BASER ... GITS_BASER + 0x3f:
+ /*
+ * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is
+ * already enabled
+ */
+ if (!(s->ctlr & ITS_CTLR_ENABLED)) {
+ index = (offset - GITS_BASER) / 8;
+
+ if (offset & 7) {
+ value <<= 32;
+ value &= ~GITS_BASER_RO_MASK;
+ s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(0, 32);
+ s->baser[index] |= value;
+ } else {
+ value &= ~GITS_BASER_RO_MASK;
+ s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(32, 32);
+ s->baser[index] |= value;
+ }
+ }
+ break;
+ case GITS_IIDR:
+ case GITS_IDREGS ... GITS_IDREGS + 0x2f:
+ /* RO registers, ignore the write */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write to RO register at offset "
+ TARGET_FMT_plx "\n", __func__, offset);
+ break;
+ default:
+ result = MEMTX_ERROR;
+ break;
+ }
return result;
}
@@ -49,7 +295,55 @@ static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
uint64_t *data, MemTxAttrs attrs)
{
MemTxResult result = MEMTX_OK;
+ int index;
+ switch (offset) {
+ case GITS_CTLR:
+ *data = s->ctlr;
+ break;
+ case GITS_IIDR:
+ *data = gicv3_iidr();
+ break;
+ case GITS_IDREGS ... GITS_IDREGS + 0x2f:
+ /* ID registers */
+ *data = gicv3_idreg(offset - GITS_IDREGS);
+ break;
+ case GITS_TYPER:
+ *data = extract64(s->typer, 0, 32);
+ break;
+ case GITS_TYPER + 4:
+ *data = extract64(s->typer, 32, 32);
+ break;
+ case GITS_CBASER:
+ *data = extract64(s->cbaser, 0, 32);
+ break;
+ case GITS_CBASER + 4:
+ *data = extract64(s->cbaser, 32, 32);
+ break;
+ case GITS_CREADR:
+ *data = extract64(s->creadr, 0, 32);
+ break;
+ case GITS_CREADR + 4:
+ *data = extract64(s->creadr, 32, 32);
+ break;
+ case GITS_CWRITER:
+ *data = extract64(s->cwriter, 0, 32);
+ break;
+ case GITS_CWRITER + 4:
+ *data = extract64(s->cwriter, 32, 32);
+ break;
+ case GITS_BASER ... GITS_BASER + 0x3f:
+ index = (offset - GITS_BASER) / 8;
+ if (offset & 7) {
+ *data = extract64(s->baser[index], 32, 32);
+ } else {
+ *data = extract64(s->baser[index], 0, 32);
+ }
+ break;
+ default:
+ result = MEMTX_ERROR;
+ break;
+ }
return result;
}
@@ -57,7 +351,54 @@ static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
uint64_t value, MemTxAttrs attrs)
{
MemTxResult result = MEMTX_OK;
+ int index;
+ switch (offset) {
+ case GITS_BASER ... GITS_BASER + 0x3f:
+ /*
+ * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is
+ * already enabled
+ */
+ if (!(s->ctlr & ITS_CTLR_ENABLED)) {
+ index = (offset - GITS_BASER) / 8;
+ s->baser[index] &= GITS_BASER_RO_MASK;
+ s->baser[index] |= (value & ~GITS_BASER_RO_MASK);
+ }
+ break;
+ case GITS_CBASER:
+ /*
+ * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
+ * already enabled
+ */
+ if (!(s->ctlr & ITS_CTLR_ENABLED)) {
+ s->cbaser = value;
+ s->creadr = 0;
+ s->cwriter = s->creadr;
+ }
+ break;
+ case GITS_CWRITER:
+ s->cwriter = value & ~R_GITS_CWRITER_RETRY_MASK;
+ break;
+ case GITS_CREADR:
+ if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
+ s->creadr = value & ~R_GITS_CREADR_STALLED_MASK;
+ } else {
+ /* RO register, ignore the write */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write to RO register at offset "
+ TARGET_FMT_plx "\n", __func__, offset);
+ }
+ break;
+ case GITS_TYPER:
+ /* RO registers, ignore the write */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write to RO register at offset "
+ TARGET_FMT_plx "\n", __func__, offset);
+ break;
+ default:
+ result = MEMTX_ERROR;
+ break;
+ }
return result;
}
@@ -65,7 +406,29 @@ static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
uint64_t *data, MemTxAttrs attrs)
{
MemTxResult result = MEMTX_OK;
+ int index;
+ switch (offset) {
+ case GITS_TYPER:
+ *data = s->typer;
+ break;
+ case GITS_BASER ... GITS_BASER + 0x3f:
+ index = (offset - GITS_BASER) / 8;
+ *data = s->baser[index];
+ break;
+ case GITS_CBASER:
+ *data = s->cbaser;
+ break;
+ case GITS_CREADR:
+ *data = s->creadr;
+ break;
+ case GITS_CWRITER:
+ *data = s->cwriter;
+ break;
+ default:
+ result = MEMTX_ERROR;
+ break;
+ }
return result;
}
@@ -162,6 +525,9 @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops);
if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
+ address_space_init(&s->gicv3->dma_as, s->gicv3->dma,
+ "gicv3-its-sysmem");
+
/* set the ITS default features supported */
s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
GITS_TYPE_PHYSICAL);
@@ -208,6 +574,14 @@ static void gicv3_its_reset(DeviceState *dev)
}
}
+static void gicv3_its_post_load(GICv3ITSState *s)
+{
+ if (s->ctlr & ITS_CTLR_ENABLED) {
+ extract_table_params(s);
+ extract_cmdq_params(s);
+ }
+}
+
static Property gicv3_its_props[] = {
DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3",
GICv3State *),
@@ -218,10 +592,12 @@ static void gicv3_its_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
+ GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
dc->realize = gicv3_arm_its_realize;
device_class_set_props(dc, gicv3_its_props);
device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
+ icc->post_load = gicv3_its_post_load;
}
static const TypeInfo gicv3_its_info = {
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index e0b06930a7..dc2c1bc45b 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -238,7 +238,7 @@ FIELD(GITS_BASER, PAGESIZE, 8, 2)
FIELD(GITS_BASER, SHAREABILITY, 10, 2)
FIELD(GITS_BASER, PHYADDR, 12, 36)
FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
-FIELD(GITS_BASER, PHYADDRH_64K, 48, 4)
+FIELD(GITS_BASER, PHYADDRH_64K, 12, 4)
FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
FIELD(GITS_BASER, OUTERCACHE, 53, 3)
FIELD(GITS_BASER, TYPE, 56, 3)
@@ -246,6 +246,20 @@ FIELD(GITS_BASER, INNERCACHE, 59, 3)
FIELD(GITS_BASER, INDIRECT, 62, 1)
FIELD(GITS_BASER, VALID, 63, 1)
+FIELD(GITS_CBASER, SIZE, 0, 8)
+FIELD(GITS_CBASER, SHAREABILITY, 10, 2)
+FIELD(GITS_CBASER, PHYADDR, 12, 40)
+FIELD(GITS_CBASER, OUTERCACHE, 53, 3)
+FIELD(GITS_CBASER, INNERCACHE, 59, 3)
+FIELD(GITS_CBASER, VALID, 63, 1)
+
+FIELD(GITS_CREADR, STALLED, 0, 1)
+FIELD(GITS_CREADR, OFFSET, 5, 15)
+
+FIELD(GITS_CWRITER, RETRY, 0, 1)
+FIELD(GITS_CWRITER, OFFSET, 5, 15)
+
+FIELD(GITS_CTLR, ENABLED, 0, 1)
FIELD(GITS_CTLR, QUIESCENT, 31, 1)
FIELD(GITS_TYPER, PHYSICAL, 0, 1)
@@ -257,6 +271,13 @@ FIELD(GITS_TYPER, PTA, 19, 1)
FIELD(GITS_TYPER, CIDBITS, 32, 4)
FIELD(GITS_TYPER, CIL, 36, 1)
+#define GITS_IDREGS 0xFFD0
+
+#define ITS_CTLR_ENABLED (1U) /* ITS Enabled */
+
+#define GITS_BASER_RO_MASK (R_GITS_BASER_ENTRYSIZE_MASK | \
+ R_GITS_BASER_TYPE_MASK)
+
#define GITS_BASER_PAGESIZE_4K 0
#define GITS_BASER_PAGESIZE_16K 1
#define GITS_BASER_PAGESIZE_64K 2
@@ -264,6 +285,14 @@ FIELD(GITS_TYPER, CIL, 36, 1)
#define GITS_ITT_TYPE_DEVICE 1ULL
#define GITS_ITT_TYPE_COLLECTION 4ULL
+#define GITS_PAGE_SIZE_4K 0x1000
+#define GITS_PAGE_SIZE_16K 0x4000
+#define GITS_PAGE_SIZE_64K 0x10000
+
+#define L1TABLE_ENTRY_SIZE 8
+
+#define GITS_CMDQ_ENTRY_SIZE 32
+
/**
* Default features advertised by this version of ITS
*/
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 91491a2f66..1fd5cedbbd 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -226,6 +226,9 @@ struct GICv3State {
int dev_fd; /* kvm device fd if backed by kvm vgic support */
Error *migration_blocker;
+ MemoryRegion *dma;
+ AddressSpace dma_as;
+
/* Distributor */
/* for a GIC with the security extensions the NS banked version of this
diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
index 65d1191db1..4e79145dde 100644
--- a/include/hw/intc/arm_gicv3_its_common.h
+++ b/include/hw/intc/arm_gicv3_its_common.h
@@ -41,6 +41,25 @@
#define GITS_TRANSLATER 0x0040
+typedef struct {
+ bool valid;
+ bool indirect;
+ uint16_t entry_sz;
+ uint32_t page_sz;
+ uint32_t max_entries;
+ union {
+ uint32_t max_devids;
+ uint32_t max_collids;
+ } maxids;
+ uint64_t base_addr;
+} TableDesc;
+
+typedef struct {
+ bool valid;
+ uint32_t max_entries;
+ uint64_t base_addr;
+} CmdQDesc;
+
struct GICv3ITSState {
SysBusDevice parent_obj;
@@ -63,6 +82,10 @@ struct GICv3ITSState {
uint64_t creadr;
uint64_t baser[8];
+ TableDesc dt;
+ TableDesc ct;
+ CmdQDesc cq;
+
Error *migration_blocker;
};
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v5 03/10] hw/intc: GICv3 ITS command queue framework
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-07-06 9:31 ` Eric Auger
2021-06-30 15:31 ` [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing Shashi Mallela
` (7 subsequent siblings)
10 siblings, 1 reply; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_its.c | 305 +++++++++++++++++++++++++++++++++++++++
hw/intc/gicv3_internal.h | 37 +++++
2 files changed, 342 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 2d786a1e21..5919d8d7b1 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -49,6 +49,304 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
return result;
}
+static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
+ uint64_t rdbase)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint64_t value;
+ uint64_t l2t_addr;
+ bool valid_l2t;
+ uint32_t l2t_id;
+ uint32_t max_l2_entries;
+ uint64_t cte = 0;
+ MemTxResult res = MEMTX_OK;
+
+ if (!s->ct.valid) {
+ return res;
+ }
+
+ if (valid) {
+ /* add mapping entry to collection table */
+ cte = (valid & TABLE_ENTRY_VALID_MASK) | (rdbase << 1ULL);
+ }
+
+ /*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+ if (s->ct.indirect) {
+ l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+ value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+
+ valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+ if (valid_l2t) {
+ max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+ l2t_addr = value & ((1ULL << 51) - 1);
+
+ address_space_stq_le(as, l2t_addr +
+ ((icid % max_l2_entries) * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+ }
+ } else {
+ /* Flat level table */
+ address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+ }
+ return res;
+}
+
+static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint16_t icid;
+ uint64_t rdbase;
+ bool valid;
+ MemTxResult res = MEMTX_OK;
+ uint64_t value;
+
+ offset += NUM_BYTES_IN_DW;
+ offset += NUM_BYTES_IN_DW;
+
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+
+ icid = value & ICID_MASK;
+
+ rdbase = (value >> R_MAPC_RDBASE_SHIFT) & RDBASE_PROCNUM_MASK;
+
+ valid = (value & CMD_FIELD_VALID_MASK);
+
+ if ((icid > s->ct.maxids.max_collids) || (rdbase > s->gicv3->num_cpu)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS MAPC: invalid collection table attributes "
+ "icid %d rdbase %lu\n", icid, rdbase);
+ /*
+ * in this implementation, in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+ } else {
+ res = update_cte(s, icid, valid, rdbase);
+ }
+
+ return res;
+}
+
+static MemTxResult update_dte(GICv3ITSState *s, uint32_t devid, bool valid,
+ uint8_t size, uint64_t itt_addr)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint64_t value;
+ uint64_t l2t_addr;
+ bool valid_l2t;
+ uint32_t l2t_id;
+ uint32_t max_l2_entries;
+ uint64_t dte = 0;
+ MemTxResult res = MEMTX_OK;
+
+ if (s->dt.valid) {
+ if (valid) {
+ /* add mapping entry to device table */
+ dte = (valid & TABLE_ENTRY_VALID_MASK) |
+ ((size & SIZE_MASK) << 1U) |
+ ((itt_addr & ITTADDR_MASK) << 6ULL);
+ }
+ } else {
+ return res;
+ }
+
+ /*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+ if (s->dt.indirect) {
+ l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
+
+ value = address_space_ldq_le(as,
+ s->dt.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+
+ valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+ if (valid_l2t) {
+ max_l2_entries = s->dt.page_sz / s->dt.entry_sz;
+
+ l2t_addr = value & ((1ULL << 51) - 1);
+
+ address_space_stq_le(as, l2t_addr +
+ ((devid % max_l2_entries) * GITS_DTE_SIZE),
+ dte, MEMTXATTRS_UNSPECIFIED, &res);
+ }
+ } else {
+ /* Flat level table */
+ address_space_stq_le(as, s->dt.base_addr + (devid * GITS_DTE_SIZE),
+ dte, MEMTXATTRS_UNSPECIFIED, &res);
+ }
+ return res;
+}
+
+static MemTxResult process_mapd(GICv3ITSState *s, uint64_t value,
+ uint32_t offset)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint32_t devid;
+ uint8_t size;
+ uint64_t itt_addr;
+ bool valid;
+ MemTxResult res = MEMTX_OK;
+
+ devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
+
+ offset += NUM_BYTES_IN_DW;
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+
+ size = (value & SIZE_MASK);
+
+ offset += NUM_BYTES_IN_DW;
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+
+ itt_addr = (value & ITTADDR_MASK) >> ITTADDR_SHIFT;
+
+ valid = (value & CMD_FIELD_VALID_MASK);
+
+ if ((devid > s->dt.maxids.max_devids) ||
+ (size > FIELD_EX64(s->typer, GITS_TYPER, IDBITS))) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS MAPD: invalid device table attributes "
+ "devid %d or size %d\n", devid, size);
+ /*
+ * in this implementation, in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+ } else {
+ res = update_dte(s, devid, valid, size, itt_addr);
+ }
+
+ return res;
+}
+
+/*
+ * Current implementation blocks until all
+ * commands are processed
+ */
+static void process_cmdq(GICv3ITSState *s)
+{
+ uint32_t wr_offset = 0;
+ uint32_t rd_offset = 0;
+ uint32_t cq_offset = 0;
+ uint64_t data;
+ AddressSpace *as = &s->gicv3->dma_as;
+ MemTxResult res = MEMTX_OK;
+ uint8_t cmd;
+
+ if (!(s->ctlr & ITS_CTLR_ENABLED)) {
+ return;
+ }
+
+ wr_offset = FIELD_EX64(s->cwriter, GITS_CWRITER, OFFSET);
+
+ if (wr_offset > s->cq.max_entries) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid write offset "
+ "%d\n", __func__, wr_offset);
+ return;
+ }
+
+ rd_offset = FIELD_EX64(s->creadr, GITS_CREADR, OFFSET);
+
+ if (rd_offset > s->cq.max_entries) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid read offset "
+ "%d\n", __func__, rd_offset);
+ return;
+ }
+
+ while (wr_offset != rd_offset) {
+ cq_offset = (rd_offset * GITS_CMDQ_ENTRY_SIZE);
+ data = address_space_ldq_le(as, s->cq.base_addr + cq_offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+ cmd = (data & CMD_MASK);
+
+ switch (cmd) {
+ case GITS_CMD_INT:
+ break;
+ case GITS_CMD_CLEAR:
+ break;
+ case GITS_CMD_SYNC:
+ /*
+ * Current implementation makes a blocking synchronous call
+ * for every command issued earlier, hence the internal state
+ * is already consistent by the time SYNC command is executed.
+ * Hence no further processing is required for SYNC command.
+ */
+ break;
+ case GITS_CMD_MAPD:
+ res = process_mapd(s, data, cq_offset);
+ break;
+ case GITS_CMD_MAPC:
+ res = process_mapc(s, cq_offset);
+ break;
+ case GITS_CMD_MAPTI:
+ break;
+ case GITS_CMD_MAPI:
+ break;
+ case GITS_CMD_DISCARD:
+ break;
+ case GITS_CMD_INV:
+ case GITS_CMD_INVALL:
+ break;
+ default:
+ break;
+ }
+ if (res == MEMTX_OK) {
+ rd_offset++;
+ rd_offset %= s->cq.max_entries;
+ s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, OFFSET, rd_offset);
+ } else {
+ /*
+ * in this implementation, in case of dma read/write error
+ * we stall the command processing
+ */
+ s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, STALLED, 1);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: %x cmd processing failed\n", __func__, cmd);
+ break;
+ }
+ }
+}
+
/*
* This function extracts the ITS Device and Collection table specific
* parameters (like base_addr, size etc) from GITS_BASER register.
@@ -205,6 +503,7 @@ static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
extract_table_params(s);
extract_cmdq_params(s);
s->creadr = 0;
+ process_cmdq(s);
}
break;
case GITS_CBASER:
@@ -232,6 +531,9 @@ static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
case GITS_CWRITER:
s->cwriter = deposit64(s->cwriter, 0, 32,
(value & ~R_GITS_CWRITER_RETRY_MASK));
+ if (s->cwriter != s->creadr) {
+ process_cmdq(s);
+ }
break;
case GITS_CWRITER + 4:
s->cwriter = deposit64(s->cwriter, 32, 32, value);
@@ -378,6 +680,9 @@ static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
break;
case GITS_CWRITER:
s->cwriter = value & ~R_GITS_CWRITER_RETRY_MASK;
+ if (s->cwriter != s->creadr) {
+ process_cmdq(s);
+ }
break;
case GITS_CREADR:
if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index dc2c1bc45b..a27b1e4d19 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -292,6 +292,43 @@ FIELD(GITS_TYPER, CIL, 36, 1)
#define L1TABLE_ENTRY_SIZE 8
#define GITS_CMDQ_ENTRY_SIZE 32
+#define NUM_BYTES_IN_DW 8
+
+#define CMD_MASK 0xff
+
+/* ITS Commands */
+#define GITS_CMD_CLEAR 0x04
+#define GITS_CMD_DISCARD 0x0F
+#define GITS_CMD_INT 0x03
+#define GITS_CMD_MAPC 0x09
+#define GITS_CMD_MAPD 0x08
+#define GITS_CMD_MAPI 0x0B
+#define GITS_CMD_MAPTI 0x0A
+#define GITS_CMD_INV 0x0C
+#define GITS_CMD_INVALL 0x0D
+#define GITS_CMD_SYNC 0x05
+
+/* MAPC command fields */
+#define ICID_LENGTH 16
+#define ICID_MASK ((1U << ICID_LENGTH) - 1)
+FIELD(MAPC, RDBASE, 16, 32)
+
+#define RDBASE_PROCNUM_LENGTH 16
+#define RDBASE_PROCNUM_MASK ((1ULL << RDBASE_PROCNUM_LENGTH) - 1)
+
+/* MAPD command fields */
+#define ITTADDR_LENGTH 44
+#define ITTADDR_SHIFT 8
+#define ITTADDR_MASK ((1ULL << ITTADDR_LENGTH) - 1)
+#define SIZE_MASK 0x1f
+
+#define DEVID_SHIFT 32
+#define DEVID_MASK MAKE_64BIT_MASK(32, 32)
+
+#define VALID_SHIFT 63
+#define CMD_FIELD_VALID_MASK (1ULL << VALID_SHIFT)
+#define L2_TABLE_VALID_MASK CMD_FIELD_VALID_MASK
+#define TABLE_ENTRY_VALID_MASK (1ULL << 0)
/**
* Default features advertised by this version of ITS
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
` (2 preceding siblings ...)
2021-06-30 15:31 ` [PATCH v5 03/10] hw/intc: GICv3 ITS command queue framework Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-07-05 14:07 ` Peter Maydell
` (2 more replies)
2021-06-30 15:31 ` [PATCH v5 05/10] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
` (6 subsequent siblings)
10 siblings, 3 replies; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
---
hw/intc/arm_gicv3_its.c | 361 ++++++++++++++++++++++++++++-
hw/intc/gicv3_internal.h | 26 +++
include/hw/intc/arm_gicv3_common.h | 2 +
3 files changed, 388 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 5919d8d7b1..adaee72c1f 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -28,6 +28,22 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+/*
+ * This is an internal enum used to distinguish between LPI triggered
+ * via command queue and LPI triggered via gits_translater write.
+ */
+typedef enum ItsCmdType {
+ NONE = 0, /* internal indication for GITS_TRANSLATER write */
+ CLEAR = 1,
+ DISCARD = 2,
+ INT = 3,
+} ItsCmdType;
+
+typedef struct {
+ uint32_t iteh;
+ uint64_t itel;
+} IteEntry;
+
static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
{
uint64_t result = 0;
@@ -49,6 +65,330 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
return result;
}
+static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte,
+ MemTxResult *res)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint64_t l2t_addr;
+ uint64_t value;
+ bool valid_l2t;
+ uint32_t l2t_id;
+ uint32_t max_l2_entries;
+
+ if (s->ct.indirect) {
+ l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+ value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+ if (*res == MEMTX_OK) {
+ valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+ if (valid_l2t) {
+ max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+ l2t_addr = value & ((1ULL << 51) - 1);
+
+ *cte = address_space_ldq_le(as, l2t_addr +
+ ((icid % max_l2_entries) * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+ }
+ }
+ } else {
+ /* Flat level table */
+ *cte = address_space_ldq_le(as, s->ct.base_addr +
+ (icid * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+ }
+
+ return (*cte & TABLE_ENTRY_VALID_MASK) != 0;
+}
+
+static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+ IteEntry ite)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint64_t itt_addr;
+ MemTxResult res = MEMTX_OK;
+
+ itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
+ itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+ address_space_stq_le(as, itt_addr + (eventid * sizeof(uint64_t)),
+ ite.itel, MEMTXATTRS_UNSPECIFIED, &res);
+
+ if (res == MEMTX_OK) {
+ address_space_stl_le(as, itt_addr + ((eventid + sizeof(uint64_t)) *
+ sizeof(uint32_t)), ite.iteh,
+ MEMTXATTRS_UNSPECIFIED, &res);
+ }
+ return res;
+}
+
+static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+ uint16_t *icid, uint32_t *pIntid, MemTxResult *res)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint64_t itt_addr;
+ bool status = false;
+ IteEntry ite;
+
+ itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
+ itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+ memset(&ite, 0 , sizeof(ite));
+ ite.itel = address_space_ldq_le(as, itt_addr +
+ (eventid * sizeof(uint64_t)),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+ if (*res == MEMTX_OK) {
+ ite.iteh = address_space_ldl_le(as, itt_addr + ((eventid +
+ sizeof(uint64_t)) * sizeof(uint32_t)),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+ if (*res == MEMTX_OK) {
+ if (ite.itel & TABLE_ENTRY_VALID_MASK) {
+ if ((ite.itel >> ITE_ENTRY_INTTYPE_SHIFT) &
+ GITS_TYPE_PHYSICAL) {
+ *pIntid = (ite.itel >> ITE_ENTRY_INTID_SHIFT) &
+ ITE_ENTRY_INTID_MASK;
+ *icid = ite.iteh & ITE_ENTRY_ICID_MASK;
+ status = true;
+ }
+ }
+ }
+ }
+ return status;
+}
+
+static uint64_t get_dte(GICv3ITSState *s, uint32_t devid, MemTxResult *res)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint64_t l2t_addr;
+ uint64_t value;
+ bool valid_l2t;
+ uint32_t l2t_id;
+ uint32_t max_l2_entries;
+
+ if (s->dt.indirect) {
+ l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
+
+ value = address_space_ldq_le(as,
+ s->dt.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+ if (*res == MEMTX_OK) {
+ valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+ if (valid_l2t) {
+ max_l2_entries = s->dt.page_sz / s->dt.entry_sz;
+
+ l2t_addr = value & ((1ULL << 51) - 1);
+
+ value = address_space_ldq_le(as, l2t_addr +
+ ((devid % max_l2_entries) * GITS_DTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+ }
+ }
+ } else {
+ /* Flat level table */
+ value = address_space_ldq_le(as, s->dt.base_addr +
+ (devid * GITS_DTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+ }
+
+ return value;
+}
+
+/*
+ * This function handles the processing of following commands based on
+ * the ItsCmdType parameter passed:-
+ * 1. trigerring of lpi interrupt translation via ITS INT command
+ * 2. trigerring of lpi interrupt translation via gits_translater register
+ * 3. handling of ITS CLEAR command
+ * 4. handling of ITS DISCARD command
+ */
+static MemTxResult process_its_cmd(GICv3ITSState *s, uint64_t value,
+ uint32_t offset, ItsCmdType cmd)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint32_t devid, eventid;
+ MemTxResult res = MEMTX_OK;
+ bool dte_valid;
+ uint64_t dte = 0;
+ uint32_t max_eventid;
+ uint16_t icid = 0;
+ uint32_t pIntid = 0;
+ bool ite_valid = false;
+ uint64_t cte = 0;
+ bool cte_valid = false;
+ IteEntry ite;
+
+ if (cmd == NONE) {
+ devid = offset;
+ } else {
+ devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
+
+ offset += NUM_BYTES_IN_DW;
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+ }
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+
+ eventid = (value & EVENTID_MASK);
+
+ dte = get_dte(s, devid, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+ dte_valid = dte & TABLE_ENTRY_VALID_MASK;
+
+ if (dte_valid) {
+ max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
+
+ ite_valid = get_ite(s, eventid, dte, &icid, &pIntid, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+
+ if (ite_valid) {
+ cte_valid = get_cte(s, icid, &cte, &res);
+ }
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+ }
+
+ if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid ||
+ !cte_valid || (eventid > max_eventid)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid command attributes "
+ "devid %d or eventid %d or invalid dte %d or"
+ "invalid cte %d or invalid ite %d\n",
+ __func__, devid, eventid, dte_valid, cte_valid,
+ ite_valid);
+ /*
+ * in this implementation, in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+ } else {
+ /*
+ * Current implementation only supports rdbase == procnum
+ * Hence rdbase physical address is ignored
+ */
+ if (cmd == DISCARD) {
+ memset(&ite, 0 , sizeof(ite));
+ /* remove mapping from interrupt translation table */
+ res = update_ite(s, eventid, dte, ite);
+ }
+ }
+
+ return res;
+}
+
+static MemTxResult process_mapti(GICv3ITSState *s, uint64_t value,
+ uint32_t offset, bool ignore_pInt)
+{
+ AddressSpace *as = &s->gicv3->dma_as;
+ uint32_t devid, eventid;
+ uint32_t pIntid = 0;
+ uint32_t max_eventid, max_Intid;
+ bool dte_valid;
+ MemTxResult res = MEMTX_OK;
+ uint16_t icid = 0;
+ uint64_t dte = 0;
+ IteEntry ite;
+ uint32_t int_spurious = INTID_SPURIOUS;
+ uint64_t idbits;
+
+ devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
+ offset += NUM_BYTES_IN_DW;
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+
+ eventid = (value & EVENTID_MASK);
+
+ if (!ignore_pInt) {
+ pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT);
+ }
+
+ offset += NUM_BYTES_IN_DW;
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+
+ icid = value & ICID_MASK;
+
+ dte = get_dte(s, devid, &res);
+
+ if (res != MEMTX_OK) {
+ return res;
+ }
+ dte_valid = dte & TABLE_ENTRY_VALID_MASK;
+
+ max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
+
+ if (!ignore_pInt) {
+ idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser, GICR_PROPBASER,
+ IDBITS), GICD_TYPER_IDBITS);
+
+ if (idbits < GICR_PROPBASER_IDBITS_THRESHOLD) {
+ return res;
+ }
+ max_Intid = (1ULL << (idbits + 1));
+ }
+
+ if ((devid > s->dt.maxids.max_devids) || (icid > s->ct.maxids.max_collids)
+ || !dte_valid || (eventid > max_eventid) ||
+ (!ignore_pInt && ((pIntid < GICV3_LPI_INTID_START) ||
+ (pIntid > max_Intid)))) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid command attributes "
+ "devid %d or icid %d or eventid %d or pIntid %d or"
+ "unmapped dte %d\n", __func__, devid, icid, eventid,
+ pIntid, dte_valid);
+ /*
+ * in this implementation, in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+ } else {
+ memset(&ite, 0 , sizeof(ite));
+ /* add ite entry to interrupt translation table */
+ ite.itel = (dte_valid & TABLE_ENTRY_VALID_MASK) |
+ (GITS_TYPE_PHYSICAL << ITE_ENTRY_INTTYPE_SHIFT);
+
+ if (ignore_pInt) {
+ ite.itel |= (eventid << ITE_ENTRY_INTID_SHIFT);
+ } else {
+ ite.itel |= (pIntid << ITE_ENTRY_INTID_SHIFT);
+ }
+ ite.itel |= (int_spurious << ITE_ENTRY_INTSP_SHIFT);
+ ite.iteh |= icid;
+
+ res = update_ite(s, eventid, dte, ite);
+ }
+
+ return res;
+}
+
static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
uint64_t rdbase)
{
@@ -127,7 +467,8 @@ static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
icid = value & ICID_MASK;
- rdbase = (value >> R_MAPC_RDBASE_SHIFT) & RDBASE_PROCNUM_MASK;
+ rdbase = (value & R_MAPC_RDBASE_MASK) >> R_MAPC_RDBASE_SHIFT;
+ rdbase &= RDBASE_PROCNUM_MASK;
valid = (value & CMD_FIELD_VALID_MASK);
@@ -301,8 +642,10 @@ static void process_cmdq(GICv3ITSState *s)
switch (cmd) {
case GITS_CMD_INT:
+ res = process_its_cmd(s, data, cq_offset, INT);
break;
case GITS_CMD_CLEAR:
+ res = process_its_cmd(s, data, cq_offset, CLEAR);
break;
case GITS_CMD_SYNC:
/*
@@ -319,10 +662,13 @@ static void process_cmdq(GICv3ITSState *s)
res = process_mapc(s, cq_offset);
break;
case GITS_CMD_MAPTI:
+ res = process_mapti(s, data, cq_offset, false);
break;
case GITS_CMD_MAPI:
+ res = process_mapti(s, data, cq_offset, true);
break;
case GITS_CMD_DISCARD:
+ res = process_its_cmd(s, data, cq_offset, DISCARD);
break;
case GITS_CMD_INV:
case GITS_CMD_INVALL:
@@ -484,7 +830,20 @@ static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
uint64_t data, unsigned size,
MemTxAttrs attrs)
{
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
MemTxResult result = MEMTX_OK;
+ uint32_t devid = 0;
+
+ switch (offset) {
+ case GITS_TRANSLATER:
+ if (s->ctlr & ITS_CTLR_ENABLED) {
+ devid = attrs.requester_id;
+ result = process_its_cmd(s, data, devid, NONE);
+ }
+ break;
+ default:
+ break;
+ }
return result;
}
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index a27b1e4d19..f7675a5adc 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -123,6 +123,20 @@
#define GICR_TYPER_COMMONLPIAFF (0x3 << 24)
#define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32)
+FIELD(GICR_PROPBASER, IDBITS, 0, 5)
+FIELD(GICR_PROPBASER, INNERCACHE, 7, 3)
+FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2)
+FIELD(GICR_PROPBASER, PHYADDR, 12, 40)
+FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3)
+
+#define GICR_PROPBASER_IDBITS_THRESHOLD 0xd
+
+FIELD(GICR_PENDBASER, INNERCACHE, 7, 3)
+FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2)
+FIELD(GICR_PENDBASER, PHYADDR, 16, 36)
+FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3)
+FIELD(GICR_PENDBASER, PTZ, 62, 1)
+
#define GICR_WAKER_ProcessorSleep (1U << 1)
#define GICR_WAKER_ChildrenAsleep (1U << 2)
@@ -322,6 +336,13 @@ FIELD(MAPC, RDBASE, 16, 32)
#define ITTADDR_MASK ((1ULL << ITTADDR_LENGTH) - 1)
#define SIZE_MASK 0x1f
+/* MAPI command fields */
+#define EVENTID_MASK ((1ULL << 32) - 1)
+
+/* MAPTI command fields */
+#define pINTID_SHIFT 32
+#define pINTID_MASK MAKE_64BIT_MASK(32, 32)
+
#define DEVID_SHIFT 32
#define DEVID_MASK MAKE_64BIT_MASK(32, 32)
@@ -347,6 +368,11 @@ FIELD(MAPC, RDBASE, 16, 32)
* vPEID = 16 bits
*/
#define ITS_ITT_ENTRY_SIZE 0xC
+#define ITE_ENTRY_INTTYPE_SHIFT 1
+#define ITE_ENTRY_INTID_SHIFT 2
+#define ITE_ENTRY_INTID_MASK ((1ULL << 24) - 1)
+#define ITE_ENTRY_INTSP_SHIFT 26
+#define ITE_ENTRY_ICID_MASK ((1ULL << 16) - 1)
/* 16 bits EventId */
#define ITS_IDBITS GICD_TYPER_IDBITS
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 1fd5cedbbd..0715b0bc2a 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -36,6 +36,8 @@
#define GICV3_MAXIRQ 1020
#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
+#define GICV3_LPI_INTID_START 8192
+
#define GICV3_REDIST_SIZE 0x20000
/* Number of SGI target-list bits */
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v5 05/10] hw/intc: GICv3 ITS Feature enablement
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
` (3 preceding siblings ...)
2021-06-30 15:31 ` [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-07-05 14:20 ` Peter Maydell
2021-06-30 15:31 ` [PATCH v5 06/10] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
` (5 subsequent siblings)
10 siblings, 1 reply; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
---
hw/intc/arm_gicv3_common.c | 12 ++++++++++++
hw/intc/arm_gicv3_dist.c | 5 ++++-
hw/intc/arm_gicv3_redist.c | 12 +++++++++---
hw/intc/gicv3_internal.h | 9 ++++++---
include/hw/intc/arm_gicv3_common.h | 1 +
5 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 58ef65f589..53dea2a775 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
return;
}
+ if (s->lpi_enable && !s->dma) {
+ error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
+ return;
+ }
+
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
@@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
(1 << 24) |
(i << 8) |
(last << 4);
+
+ if (s->lpi_enable) {
+ s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
+ }
}
}
@@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
+ DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
redist_region_count, qdev_prop_uint32, uint32_t),
+ DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
+ MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f903..ae625d758a 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -371,7 +371,9 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
* A3V == 1 (non-zero values of Affinity level 3 supported)
* IDbits == 0xf (we support 16-bit interrupt identifiers)
* DVIS == 0 (Direct virtual LPI injection not supported)
- * LPIS == 0 (LPIs not supported)
+ * LPIS == 1 (LPIs are supported if affinity routing is enabled)
+ * num_LPIs == 0b00000 (bits [15:11],Number of LPIs as indicated
+ * by GICD_TYPER.IDbits)
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
* CPUNumber == 0 since for us ARE is always 1
@@ -386,6 +388,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
+ (s->lpi_enable << GICD_TYPER_LPIS_OFFSET) |
(0xf << 19) | itlinesnumber;
return MEMTX_OK;
}
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 8645220d61..fc3d95dcc6 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
case GICR_CTLR:
/* For our implementation, GICR_TYPER.DPGS is 0 and so all
* the DPG bits are RAZ/WI. We don't do anything asynchronously,
- * so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't
- * implement LPIs) so Enable_LPIs is RES0. So there are no writable
- * bits for us.
+ * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
+ * implement LPIs) so Enable_LPIs is programmable.
*/
+ if (cs->gicr_typer & GICR_TYPER_PLPIS) {
+ if (value & GICR_CTLR_ENABLE_LPIS) {
+ cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
+ } else {
+ cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
+ }
+ }
return MEMTX_OK;
case GICR_STATUSR:
/* RAZ/WI for our implementation */
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index f7675a5adc..43ce4a8a95 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -68,6 +68,9 @@
#define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_RWP (1U << 31)
+#define GICD_TYPER_LPIS_OFFSET 17
+#define GICD_TYPER_IDBITS_OFFSET 19
+#define GICD_TYPER_IDBITS_MASK 0x1f
/* 16 bits EventId */
#define GICD_TYPER_IDBITS 0xf
@@ -123,6 +126,9 @@
#define GICR_TYPER_COMMONLPIAFF (0x3 << 24)
#define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32)
+#define GICR_WAKER_ProcessorSleep (1U << 1)
+#define GICR_WAKER_ChildrenAsleep (1U << 2)
+
FIELD(GICR_PROPBASER, IDBITS, 0, 5)
FIELD(GICR_PROPBASER, INNERCACHE, 7, 3)
FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2)
@@ -137,9 +143,6 @@ FIELD(GICR_PENDBASER, PHYADDR, 16, 36)
FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3)
FIELD(GICR_PENDBASER, PTZ, 62, 1)
-#define GICR_WAKER_ProcessorSleep (1U << 1)
-#define GICR_WAKER_ChildrenAsleep (1U << 2)
-
#define ICC_CTLR_EL1_CBPR (1U << 0)
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
#define ICC_CTLR_EL1_PMHE (1U << 6)
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 0715b0bc2a..c1348cc60a 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -221,6 +221,7 @@ struct GICv3State {
uint32_t num_cpu;
uint32_t num_irq;
uint32_t revision;
+ bool lpi_enable;
bool security_extn;
bool irq_reset_nonsecure;
bool gicd_no_migration_shift_bug;
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v5 06/10] hw/intc: GICv3 redistributor ITS processing
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
` (4 preceding siblings ...)
2021-06-30 15:31 ` [PATCH v5 05/10] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-07-05 14:43 ` Peter Maydell
2021-06-30 15:31 ` [PATCH v5 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela
` (4 subsequent siblings)
10 siblings, 1 reply; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
---
hw/intc/arm_gicv3.c | 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c | 24 ++++-
hw/intc/arm_gicv3_redist.c | 142 +++++++++++++++++++++++++++++
hw/intc/gicv3_internal.h | 8 ++
include/hw/intc/arm_gicv3_common.h | 7 ++
7 files changed, 197 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index d63f8af604..3f24707838 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -165,6 +165,16 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
}
+ if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
+ (cs->hpplpi.prio != 0xff)) {
+ if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+ cs->hppi.irq = cs->hpplpi.irq;
+ cs->hppi.prio = cs->hpplpi.prio;
+ cs->hppi.grp = cs->hpplpi.grp;
+ seenbetter = true;
+ }
+ }
+
/* If the best interrupt we just found would preempt whatever
* was the previous best interrupt before this update, then
* we know it's definitely the best one now.
@@ -339,9 +349,13 @@ static void gicv3_set_irq(void *opaque, int irq, int level)
static void arm_gicv3_post_load(GICv3State *s)
{
+ int i;
/* Recalculate our cached idea of the current highest priority
* pending interrupt, but don't set IRQ or FIQ lines.
*/
+ for (i = 0; i < s->num_cpu; i++) {
+ gicv3_redist_update_lpi(&s->cpu[i]);
+ }
gicv3_full_update_noirqset(s);
/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
gicv3_cache_all_target_cpustates(s);
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 53dea2a775..223db16fec 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState *dev)
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
cs->hppi.prio = 0xff;
+ cs->hpplpi.prio = 0xff;
/* State in the CPU interface must *not* be reset here, because it
* is part of the CPU's reset domain, not the GIC device's.
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 3e0641aff9..184b92e7de 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -899,10 +899,12 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
gicv3_redist_update(cs);
- } else {
+ } else if (irq < GICV3_LPI_INTID_START) {
gicv3_gicd_active_set(cs->gic, irq);
gicv3_gicd_pending_clear(cs->gic, irq);
gicv3_update(cs->gic, irq, 1);
+ } else {
+ gicv3_redist_lpi_pending(cs, irq, 0);
}
}
@@ -1318,7 +1320,8 @@ static void icc_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1,
gicv3_redist_affid(cs), value);
- if (irq >= cs->gic->num_irq) {
+ if ((irq >= cs->gic->num_irq) &&
+ !(cs->gic->lpi_enable && (irq >= GICV3_LPI_INTID_START))) {
/* This handles two cases:
* 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
* to the GICC_EOIR, the GIC ignores that write.
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index adaee72c1f..5adb55a01a 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -225,6 +225,7 @@ static MemTxResult process_its_cmd(GICv3ITSState *s, uint64_t value,
bool ite_valid = false;
uint64_t cte = 0;
bool cte_valid = false;
+ uint64_t rdbase;
IteEntry ite;
if (cmd == NONE) {
@@ -282,10 +283,18 @@ static MemTxResult process_its_cmd(GICv3ITSState *s, uint64_t value,
* command in the queue
*/
} else {
- /*
- * Current implementation only supports rdbase == procnum
- * Hence rdbase physical address is ignored
- */
+ rdbase = (cte >> 1U) & RDBASE_PROCNUM_MASK;
+
+ if (rdbase > s->gicv3->num_cpu) {
+ return res;
+ }
+
+ if ((cmd == CLEAR) || (cmd == DISCARD)) {
+ gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 0);
+ } else {
+ gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 1);
+ }
+
if (cmd == DISCARD) {
memset(&ite, 0 , sizeof(ite));
/* remove mapping from interrupt translation table */
@@ -672,6 +681,13 @@ static void process_cmdq(GICv3ITSState *s)
break;
case GITS_CMD_INV:
case GITS_CMD_INVALL:
+ /*
+ * Current implementation doesn't cache any ITS tables,
+ * but the calculated lpi priority information.We only
+ * need to trigger lpi priority re-calculation to be in
+ * sync with LPI config table or pending table changes.
+ */
+ gicv3_redist_update_lpi(s->gicv3->cpu);
break;
default:
break;
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index fc3d95dcc6..97553e6ada 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -254,6 +254,9 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
if (cs->gicr_typer & GICR_TYPER_PLPIS) {
if (value & GICR_CTLR_ENABLE_LPIS) {
cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
+ /* Check for any pending interr in pending table */
+ gicv3_redist_update_lpi(cs);
+ gicv3_redist_update(cs);
} else {
cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
}
@@ -532,6 +535,145 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
return r;
}
+static void gicv3_redist_check_lpi_priority(GICv3CPUState *cs, int irq)
+{
+ AddressSpace *as = &cs->gic->dma_as;
+ uint64_t lpict_baddr;
+ uint8_t lpite;
+ uint8_t prio;
+
+ lpict_baddr = cs->gicr_propbaser & R_GICR_PROPBASER_PHYADDR_MASK;
+
+ address_space_read(as, lpict_baddr + ((irq - GICV3_LPI_INTID_START) *
+ sizeof(lpite)), MEMTXATTRS_UNSPECIFIED, &lpite,
+ sizeof(lpite));
+
+ if (!(lpite & LPI_CTE_ENABLED)) {
+ return;
+ }
+
+ if (cs->gic->gicd_ctlr & GICD_CTLR_DS) {
+ prio = lpite & LPI_PRIORITY_MASK;
+ } else {
+ prio = ((lpite & LPI_PRIORITY_MASK) >> 1) & 0x80;
+ }
+
+ if ((prio < cs->hpplpi.prio) ||
+ ((prio == cs->hpplpi.prio) && (irq <= cs->hpplpi.irq))) {
+ cs->hpplpi.irq = irq;
+ cs->hpplpi.prio = prio;
+ /* LPIs are always non-secure Grp1 interrupts */
+ cs->hpplpi.grp = GICV3_G1NS;
+ }
+}
+
+void gicv3_redist_update_lpi(GICv3CPUState *cs)
+{
+ /*
+ * This function scans the LPI pending table and for each pending
+ * LPI, reads the corresponding entry from LPI configuration table
+ * to extract the priority info and determine if the current LPI
+ * priority is lower than the last computed high priority lpi interrupt.
+ * If yes, replace current LPI as the new high priority lpi interrupt.
+ */
+ AddressSpace *as = &cs->gic->dma_as;
+ uint64_t lpipt_baddr;
+ uint32_t pendt_size = 0;
+ uint8_t pend;
+ int i;
+ uint64_t idbits;
+
+ idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS),
+ GICD_TYPER_IDBITS);
+
+ if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser ||
+ !cs->gicr_pendbaser || (idbits < GICR_PROPBASER_IDBITS_THRESHOLD)) {
+ return;
+ }
+
+ cs->hpplpi.prio = 0xff;
+
+ lpipt_baddr = cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK;
+
+ /* Determine the highest priority pending interrupt among LPIs */
+ pendt_size = (1ULL << (idbits + 1));
+
+ for (i = 0; i < pendt_size / 8; i++) {
+ address_space_read(as, lpipt_baddr +
+ (((GICV3_LPI_INTID_START + i) / 8) * sizeof(pend)),
+ MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend));
+
+ if (!((1 << ((GICV3_LPI_INTID_START + i) % 8)) & pend)) {
+ continue;
+ }
+
+ gicv3_redist_check_lpi_priority(cs, GICV3_LPI_INTID_START + i);
+ }
+}
+
+void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level)
+{
+ /*
+ * This function updates the pending bit in lpi pending table for
+ * the irq being activated or deactivated.
+ */
+ AddressSpace *as = &cs->gic->dma_as;
+ uint64_t lpipt_baddr;
+ bool ispend = false;
+ uint8_t pend;
+
+ /*
+ * get the bit value corresponding to this irq in the
+ * lpi pending table
+ */
+ lpipt_baddr = cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK;
+
+ address_space_read(as, lpipt_baddr + ((irq / 8) * sizeof(pend)),
+ MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend));
+
+ /*
+ * check if this LPI is better than the current hpplpi, if yes
+ * just set hpplpi.prio and .irq without doing a full rescan
+ */
+ if (level) {
+ gicv3_redist_check_lpi_priority(cs, irq);
+ }
+
+ ispend = extract32(pend, irq % 8, 1);
+
+ /* no change in the value of pending bit,return */
+ if (ispend == level) {
+ return;
+ }
+ pend = deposit32(pend, irq % 8, 1, level ? 1 : 0);
+
+ address_space_write(as, lpipt_baddr + ((irq / 8) * sizeof(pend)),
+ MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend));
+
+ if (!level) {
+ gicv3_redist_update_lpi(cs);
+ }
+}
+
+void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level)
+{
+ uint64_t idbits;
+
+ idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS),
+ GICD_TYPER_IDBITS);
+
+ if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser ||
+ !cs->gicr_pendbaser || (idbits < GICR_PROPBASER_IDBITS_THRESHOLD) ||
+ (irq > (1ULL << (idbits + 1)))) {
+ return;
+ }
+
+ /* set/clear the pending bit for this irq */
+ gicv3_redist_lpi_pending(cs, irq, level);
+
+ gicv3_redist_update(cs);
+}
+
void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level)
{
/* Update redistributor state for a change in an external PPI input line */
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 43ce4a8a95..c0ec1d9a66 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -308,6 +308,11 @@ FIELD(GITS_TYPER, CIL, 36, 1)
#define L1TABLE_ENTRY_SIZE 8
+#define LPI_CTE_ENABLED TABLE_ENTRY_VALID_MASK
+#define LPI_CTE_PRIORITY_OFFSET 2
+#define LPI_CTE_PRIORITY_MASK ((1U << 6) - 1)
+#define LPI_PRIORITY_MASK 0xfc
+
#define GITS_CMDQ_ENTRY_SIZE 32
#define NUM_BYTES_IN_DW 8
@@ -455,6 +460,9 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size, MemTxAttrs attrs);
void gicv3_dist_set_irq(GICv3State *s, int irq, int level);
void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level);
+void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level);
+void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level);
+void gicv3_redist_update_lpi(GICv3CPUState *cs);
void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);
void gicv3_init_cpuif(GICv3State *s);
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index c1348cc60a..aa4f0d6770 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -204,6 +204,13 @@ struct GICv3CPUState {
* real state above; it doesn't need to be migrated.
*/
PendingIrq hppi;
+
+ /*
+ * Cached information recalculated from LPI tables
+ * in guest memory
+ */
+ PendingIrq hpplpi;
+
/* This is temporary working state, to avoid a malloc in gicv3_update() */
bool seenbetter;
};
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v5 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
` (5 preceding siblings ...)
2021-06-30 15:31 ` [PATCH v5 06/10] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-07-05 14:59 ` Peter Maydell
2021-06-30 15:31 ` [PATCH v5 08/10] tests/data/acpi/virt: Add IORT files for ITS Shashi Mallela
` (3 subsequent siblings)
10 siblings, 1 reply; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
---
hw/arm/sbsa-ref.c | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 43c19b4923..3d9c073636 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -34,7 +34,7 @@
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
-#include "hw/intc/arm_gicv3_common.h"
+#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/loader.h"
#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
@@ -64,6 +64,7 @@ enum {
SBSA_CPUPERIPHS,
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
+ SBSA_GIC_ITS,
SBSA_SECURE_EC,
SBSA_GWDT,
SBSA_GWDT_REFRESH,
@@ -107,6 +108,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
[SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
[SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
+ [SBSA_GIC_ITS] = { 0x44090000, 0x00020000 },
[SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
[SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
@@ -377,7 +379,20 @@ static void create_secure_ram(SBSAMachineState *sms,
memory_region_add_subregion(secure_sysmem, base, secram);
}
-static void create_gic(SBSAMachineState *sms)
+static void create_its(SBSAMachineState *sms)
+{
+ DeviceState *dev;
+
+ dev = qdev_new(TYPE_ARM_GICV3_ITS);
+ SysBusDevice *s = SYS_BUS_DEVICE(dev);
+
+ object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
+ &error_abort);
+ sysbus_realize_and_unref(s, &error_fatal);
+ sysbus_mmio_map(s, 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
+}
+
+static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
{
unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
SysBusDevice *gicbusdev;
@@ -404,6 +419,10 @@ static void create_gic(SBSAMachineState *sms)
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
+ object_property_set_link(OBJECT(sms->gic), "sysmem", OBJECT(mem),
+ &error_fatal);
+ qdev_prop_set_bit(sms->gic, "has-lpi", true);
+
gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
@@ -450,6 +469,7 @@ static void create_gic(SBSAMachineState *sms)
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
+ create_its(sms);
}
static void create_uart(const SBSAMachineState *sms, int uart,
@@ -762,7 +782,7 @@ static void sbsa_ref_init(MachineState *machine)
create_secure_ram(sms, secure_sysmem);
- create_gic(sms);
+ create_gic(sms, sysmem);
create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v5 08/10] tests/data/acpi/virt: Add IORT files for ITS
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
` (6 preceding siblings ...)
2021-06-30 15:31 ` [PATCH v5 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 09/10] hw/arm/virt: add ITS support in virt GIC Shashi Mallela
` (2 subsequent siblings)
10 siblings, 0 replies; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
---
tests/data/acpi/virt/IORT | 0
tests/data/acpi/virt/IORT.memhp | 0
tests/data/acpi/virt/IORT.numamem | 0
tests/data/acpi/virt/IORT.pxb | 0
tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++
5 files changed, 4 insertions(+)
create mode 100644 tests/data/acpi/virt/IORT
create mode 100644 tests/data/acpi/virt/IORT.memhp
create mode 100644 tests/data/acpi/virt/IORT.numamem
create mode 100644 tests/data/acpi/virt/IORT.pxb
diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..2ef211df59 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,5 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/virt/IORT",
+"tests/data/acpi/virt/IORT.memhp",
+"tests/data/acpi/virt/IORT.numamem",
+"tests/data/acpi/virt/IORT.pxb",
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v5 09/10] hw/arm/virt: add ITS support in virt GIC
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
` (7 preceding siblings ...)
2021-06-30 15:31 ` [PATCH v5 08/10] tests/data/acpi/virt: Add IORT files for ITS Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 10/10] tests/data/acpi/virt: Update IORT files for ITS Shashi Mallela
2021-07-05 15:05 ` [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Peter Maydell
10 siblings, 0 replies; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 28 ++++++++++++++++++++++++++--
include/hw/arm/virt.h | 2 ++
target/arm/kvm_arm.h | 4 ++--
3 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4b96f06014..1d8c44685c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -583,6 +583,12 @@ static void create_its(VirtMachineState *vms)
const char *itsclass = its_class_name();
DeviceState *dev;
+ if (!strcmp(itsclass, "arm-gicv3-its")) {
+ if (!vms->tcg_its) {
+ itsclass = NULL;
+ }
+ }
+
if (!itsclass) {
/* Do nothing if not supported */
return;
@@ -620,7 +626,7 @@ static void create_v2m(VirtMachineState *vms)
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
}
-static void create_gic(VirtMachineState *vms)
+static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
{
MachineState *ms = MACHINE(vms);
/* We create a standalone GIC */
@@ -654,6 +660,14 @@ static void create_gic(VirtMachineState *vms)
nb_redist_regions);
qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
+ if (!kvm_irqchip_in_kernel()) {
+ if (vms->tcg_its) {
+ object_property_set_link(OBJECT(vms->gic), "sysmem",
+ OBJECT(mem), &error_fatal);
+ qdev_prop_set_bit(vms->gic, "has-lpi", true);
+ }
+ }
+
if (nb_redist_regions == 2) {
uint32_t redist1_capacity =
vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
@@ -2039,7 +2053,7 @@ static void machvirt_init(MachineState *machine)
virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
- create_gic(vms);
+ create_gic(vms, sysmem);
virt_cpu_post_init(vms, sysmem);
@@ -2720,6 +2734,12 @@ static void virt_instance_init(Object *obj)
} else {
/* Default allows ITS instantiation */
vms->its = true;
+
+ if (vmc->no_tcg_its) {
+ vms->tcg_its = false;
+ } else {
+ vms->tcg_its = true;
+ }
}
/* Default disallows iommu instantiation */
@@ -2766,8 +2786,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
static void virt_machine_6_0_options(MachineClass *mc)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_6_1_options(mc);
compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
+ /* qemu ITS was introduced with 6.1 */
+ vmc->no_tcg_its = true;
}
DEFINE_VIRT_MACHINE(6, 0)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 921416f918..f873ab9068 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -120,6 +120,7 @@ struct VirtMachineClass {
MachineClass parent;
bool disallow_affinity_adjustment;
bool no_its;
+ bool no_tcg_its;
bool no_pmu;
bool claim_edge_triggered_timers;
bool smbios_old_sys_ver;
@@ -141,6 +142,7 @@ struct VirtMachineState {
bool highmem;
bool highmem_ecam;
bool its;
+ bool tcg_its;
bool virt;
bool ras;
bool mte;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 34f8daa377..0613454975 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -525,8 +525,8 @@ static inline const char *its_class_name(void)
/* KVM implementation requires this capability */
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
} else {
- /* Software emulation is not implemented yet */
- return NULL;
+ /* Software emulation based model */
+ return "arm-gicv3-its";
}
}
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v5 10/10] tests/data/acpi/virt: Update IORT files for ITS
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
` (8 preceding siblings ...)
2021-06-30 15:31 ` [PATCH v5 09/10] hw/arm/virt: add ITS support in virt GIC Shashi Mallela
@ 2021-06-30 15:31 ` Shashi Mallela
2021-07-05 15:02 ` Peter Maydell
2021-07-05 15:05 ` [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Peter Maydell
10 siblings, 1 reply; 41+ messages in thread
From: Shashi Mallela @ 2021-06-30 15:31 UTC (permalink / raw)
To: peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
Updated expected IORT files applicable with latest GICv3
ITS changes.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
---
tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 4 ----
5 files changed, 4 deletions(-)
diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644
GIT binary patch
literal 124
zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0#
QRGb+i3L*dhhtM#y0PN=p0RR91
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644
GIT binary patch
literal 124
zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0#
QRGb+i3L*dhhtM#y0PN=p0RR91
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644
GIT binary patch
literal 124
zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0#
QRGb+i3L*dhhtM#y0PN=p0RR91
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644
GIT binary patch
literal 124
zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0#
QRGb+i3L*dhhtM#y0PN=p0RR91
literal 0
HcmV?d00001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 2ef211df59..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,5 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/virt/IORT",
-"tests/data/acpi/virt/IORT.memhp",
-"tests/data/acpi/virt/IORT.numamem",
-"tests/data/acpi/virt/IORT.pxb",
--
2.27.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-06-30 15:31 ` [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing Shashi Mallela
@ 2021-07-05 14:07 ` Peter Maydell
2021-07-06 9:27 ` Eric Auger
2021-07-05 14:54 ` Peter Maydell
2021-07-06 10:05 ` Eric Auger
2 siblings, 1 reply; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 14:07 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>
> Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
> translation which triggers an LPI via INT command as well as write
> to GITS_TRANSLATER register,defined enum to differentiate between ITS
> command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
> Each of these commands make use of other functionalities implemented to
> get device table entry,collection table entry or interrupt translation
> table entry required for their processing.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> ---
> hw/intc/arm_gicv3_its.c | 361 ++++++++++++++++++++++++++++-
> hw/intc/gicv3_internal.h | 26 +++
> include/hw/intc/arm_gicv3_common.h | 2 +
> 3 files changed, 388 insertions(+), 1 deletion(-)
> +/*
> + * This function handles the processing of following commands based on
> + * the ItsCmdType parameter passed:-
> + * 1. trigerring of lpi interrupt translation via ITS INT command
> + * 2. trigerring of lpi interrupt translation via gits_translater register
> + * 3. handling of ITS CLEAR command
> + * 4. handling of ITS DISCARD command
> + */
"triggering"
> #define DEVID_SHIFT 32
> #define DEVID_MASK MAKE_64BIT_MASK(32, 32)
> @@ -347,6 +368,11 @@ FIELD(MAPC, RDBASE, 16, 32)
> * vPEID = 16 bits
> */
> #define ITS_ITT_ENTRY_SIZE 0xC
> +#define ITE_ENTRY_INTTYPE_SHIFT 1
> +#define ITE_ENTRY_INTID_SHIFT 2
> +#define ITE_ENTRY_INTID_MASK ((1ULL << 24) - 1)
> +#define ITE_ENTRY_INTSP_SHIFT 26
> +#define ITE_ENTRY_ICID_MASK ((1ULL << 16) - 1)
This is still using a MASK value that's at the bottom of the
integer, not in its shifted location.
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 05/10] hw/intc: GICv3 ITS Feature enablement
2021-06-30 15:31 ` [PATCH v5 05/10] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
@ 2021-07-05 14:20 ` Peter Maydell
0 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 14:20 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>
> Added properties to enable ITS feature and define qemu system
> address space memory in gicv3 common,setup distributor and
> redistributor registers to indicate LPI support.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
>
> diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
> index f7675a5adc..43ce4a8a95 100644
> --- a/hw/intc/gicv3_internal.h
> +++ b/hw/intc/gicv3_internal.h
> @@ -68,6 +68,9 @@
> #define GICD_CTLR_E1NWF (1U << 7)
> #define GICD_CTLR_RWP (1U << 31)
>
> +#define GICD_TYPER_LPIS_OFFSET 17
This should be named GICD_TYPER_LPIS_SHIFT, in the usual naming convention.
> +#define GICD_TYPER_IDBITS_OFFSET 19
> +#define GICD_TYPER_IDBITS_MASK 0x1f
You never use these, so don't define them.
> /* 16 bits EventId */
> #define GICD_TYPER_IDBITS 0xf
>
> @@ -123,6 +126,9 @@
> #define GICR_TYPER_COMMONLPIAFF (0x3 << 24)
> #define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32)
>
> +#define GICR_WAKER_ProcessorSleep (1U << 1)
> +#define GICR_WAKER_ChildrenAsleep (1U << 2)
> +
> FIELD(GICR_PROPBASER, IDBITS, 0, 5)
> FIELD(GICR_PROPBASER, INNERCACHE, 7, 3)
> FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2)
> @@ -137,9 +143,6 @@ FIELD(GICR_PENDBASER, PHYADDR, 16, 36)
> FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3)
> FIELD(GICR_PENDBASER, PTZ, 62, 1)
>
> -#define GICR_WAKER_ProcessorSleep (1U << 1)
> -#define GICR_WAKER_ChildrenAsleep (1U << 2)
> -
Why move these defines?
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 06/10] hw/intc: GICv3 redistributor ITS processing
2021-06-30 15:31 ` [PATCH v5 06/10] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
@ 2021-07-05 14:43 ` Peter Maydell
0 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 14:43 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>
> Implemented lpi processing at redistributor to get lpi config info
> from lpi configuration table,determine priority,set pending state in
> lpi pending table and forward the lpi to cpuif.Added logic to invoke
> redistributor lpi processing with translated LPI which set/clear LPI
> from ITS device as part of ITS INT,CLEAR,DISCARD command and
> GITS_TRANSLATER processing.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> ---
> hw/intc/arm_gicv3.c | 14 +++
> hw/intc/arm_gicv3_common.c | 1 +
> hw/intc/arm_gicv3_cpuif.c | 7 +-
> hw/intc/arm_gicv3_its.c | 24 ++++-
> hw/intc/arm_gicv3_redist.c | 142 +++++++++++++++++++++++++++++
> hw/intc/gicv3_internal.h | 8 ++
> include/hw/intc/arm_gicv3_common.h | 7 ++
> 7 files changed, 197 insertions(+), 6 deletions(-)
> diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> index adaee72c1f..5adb55a01a 100644
> --- a/hw/intc/arm_gicv3_its.c
> +++ b/hw/intc/arm_gicv3_its.c
> @@ -225,6 +225,7 @@ static MemTxResult process_its_cmd(GICv3ITSState *s, uint64_t value,
> bool ite_valid = false;
> uint64_t cte = 0;
> bool cte_valid = false;
> + uint64_t rdbase;
> IteEntry ite;
>
> if (cmd == NONE) {
> @@ -282,10 +283,18 @@ static MemTxResult process_its_cmd(GICv3ITSState *s, uint64_t value,
> * command in the queue
> */
> } else {
> - /*
> - * Current implementation only supports rdbase == procnum
> - * Hence rdbase physical address is ignored
> - */
This change doesn't make us start handling the "is a physical address"
case, so why delete the comment?
> + rdbase = (cte >> 1U) & RDBASE_PROCNUM_MASK;
> +
> + if (rdbase > s->gicv3->num_cpu) {
> + return res;
> + }
> +
> + if ((cmd == CLEAR) || (cmd == DISCARD)) {
> + gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 0);
> + } else {
> + gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 1);
> + }
> +
> if (cmd == DISCARD) {
> memset(&ite, 0 , sizeof(ite));
> /* remove mapping from interrupt translation table */
> @@ -672,6 +681,13 @@ static void process_cmdq(GICv3ITSState *s)
> break;
> case GITS_CMD_INV:
> case GITS_CMD_INVALL:
> + /*
> + * Current implementation doesn't cache any ITS tables,
> + * but the calculated lpi priority information.We only
Missing space after "."
> + * need to trigger lpi priority re-calculation to be in
> + * sync with LPI config table or pending table changes.
> + */
> + gicv3_redist_update_lpi(s->gicv3->cpu);
I think we need to recalculate for all redistributors, not just the first one.
> break;
> default:
> break;
> diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
> index fc3d95dcc6..97553e6ada 100644
> --- a/hw/intc/arm_gicv3_redist.c
> +++ b/hw/intc/arm_gicv3_redist.c
> @@ -254,6 +254,9 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
> if (cs->gicr_typer & GICR_TYPER_PLPIS) {
> if (value & GICR_CTLR_ENABLE_LPIS) {
> cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
> + /* Check for any pending interr in pending table */
> + gicv3_redist_update_lpi(cs);
> + gicv3_redist_update(cs);
> } else {
> cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
> }
> @@ -532,6 +535,145 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
> return r;
> }
>
> +static void gicv3_redist_check_lpi_priority(GICv3CPUState *cs, int irq)
> +{
> + AddressSpace *as = &cs->gic->dma_as;
> + uint64_t lpict_baddr;
> + uint8_t lpite;
> + uint8_t prio;
> +
> + lpict_baddr = cs->gicr_propbaser & R_GICR_PROPBASER_PHYADDR_MASK;
> +
> + address_space_read(as, lpict_baddr + ((irq - GICV3_LPI_INTID_START) *
> + sizeof(lpite)), MEMTXATTRS_UNSPECIFIED, &lpite,
> + sizeof(lpite));
> +
> + if (!(lpite & LPI_CTE_ENABLED)) {
> + return;
> + }
> +
> + if (cs->gic->gicd_ctlr & GICD_CTLR_DS) {
> + prio = lpite & LPI_PRIORITY_MASK;
> + } else {
> + prio = ((lpite & LPI_PRIORITY_MASK) >> 1) & 0x80;
Need to OR with 0x80, not AND.
> + }
> +
> + if ((prio < cs->hpplpi.prio) ||
> + ((prio == cs->hpplpi.prio) && (irq <= cs->hpplpi.irq))) {
> + cs->hpplpi.irq = irq;
> + cs->hpplpi.prio = prio;
> + /* LPIs are always non-secure Grp1 interrupts */
> + cs->hpplpi.grp = GICV3_G1NS;
> + }
> +}
> +
> +void gicv3_redist_update_lpi(GICv3CPUState *cs)
> +{
> + /*
> + * This function scans the LPI pending table and for each pending
> + * LPI, reads the corresponding entry from LPI configuration table
> + * to extract the priority info and determine if the current LPI
> + * priority is lower than the last computed high priority lpi interrupt.
> + * If yes, replace current LPI as the new high priority lpi interrupt.
> + */
> + AddressSpace *as = &cs->gic->dma_as;
> + uint64_t lpipt_baddr;
> + uint32_t pendt_size = 0;
> + uint8_t pend;
> + int i;
> + uint64_t idbits;
> +
> + idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS),
> + GICD_TYPER_IDBITS);
> +
> + if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser ||
> + !cs->gicr_pendbaser || (idbits < GICR_PROPBASER_IDBITS_THRESHOLD)) {
> + return;
> + }
> +
> + cs->hpplpi.prio = 0xff;
> +
> + lpipt_baddr = cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK;
> +
> + /* Determine the highest priority pending interrupt among LPIs */
> + pendt_size = (1ULL << (idbits + 1));
> +
> + for (i = 0; i < pendt_size / 8; i++) {
> + address_space_read(as, lpipt_baddr +
> + (((GICV3_LPI_INTID_START + i) / 8) * sizeof(pend)),
> + MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend));
> +
> + if (!((1 << ((GICV3_LPI_INTID_START + i) % 8)) & pend)) {
> + continue;
> + }
> +
> + gicv3_redist_check_lpi_priority(cs, GICV3_LPI_INTID_START + i);
> + }
> +}
> +
> +void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level)
> +{
> + /*
> + * This function updates the pending bit in lpi pending table for
> + * the irq being activated or deactivated.
> + */
> + AddressSpace *as = &cs->gic->dma_as;
> + uint64_t lpipt_baddr;
> + bool ispend = false;
> + uint8_t pend;
> +
> + /*
> + * get the bit value corresponding to this irq in the
> + * lpi pending table
> + */
> + lpipt_baddr = cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK;
> +
> + address_space_read(as, lpipt_baddr + ((irq / 8) * sizeof(pend)),
> + MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend));
> +
> + /*
> + * check if this LPI is better than the current hpplpi, if yes
> + * just set hpplpi.prio and .irq without doing a full rescan
> + */
> + if (level) {
> + gicv3_redist_check_lpi_priority(cs, irq);
> + }
> +
> + ispend = extract32(pend, irq % 8, 1);
> +
> + /* no change in the value of pending bit,return */
Missing space after comma.
> + if (ispend == level) {
> + return;
> + }
I would put the "is the level same as it already was" check before
we go off and do the priority-check, not after. Then you can do all
the handling of "the level changed" at the end, with
if (level) {
gicv3_redist_check_lpi_priority(...);
} else {
gicv3_redist_update_lpi(...);
}
Also, if this is a level == 0, you don't need to do the full rescan
of the LPI table unless the LPI being deactivated is the current
highest priority LPI.
> + pend = deposit32(pend, irq % 8, 1, level ? 1 : 0);
> +
> + address_space_write(as, lpipt_baddr + ((irq / 8) * sizeof(pend)),
> + MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend));
> +
> + if (!level) {
> + gicv3_redist_update_lpi(cs);
> + }
> +}
> +
> +void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level)
> +{
> + uint64_t idbits;
> +
> + idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS),
> + GICD_TYPER_IDBITS);
> +
> + if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser ||
> + !cs->gicr_pendbaser || (idbits < GICR_PROPBASER_IDBITS_THRESHOLD) ||
> + (irq > (1ULL << (idbits + 1)))) {
> + return;
> + }
> +
> + /* set/clear the pending bit for this irq */
> + gicv3_redist_lpi_pending(cs, irq, level);
> +
> + gicv3_redist_update(cs);
> +}
> +
> void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level)
> {
> /* Update redistributor state for a change in an external PPI input line */
> diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
> index 43ce4a8a95..c0ec1d9a66 100644
> --- a/hw/intc/gicv3_internal.h
> +++ b/hw/intc/gicv3_internal.h
> @@ -308,6 +308,11 @@ FIELD(GITS_TYPER, CIL, 36, 1)
>
> #define L1TABLE_ENTRY_SIZE 8
>
> +#define LPI_CTE_ENABLED TABLE_ENTRY_VALID_MASK
> +#define LPI_CTE_PRIORITY_OFFSET 2
> +#define LPI_CTE_PRIORITY_MASK ((1U << 6) - 1)
These aren't using the standard naming convention (_SHIFT for the
bitshift, and the _MASK should be in-place, not in the ls bits).
But you don't use the defines anyway, so you could just not bother
defining them.
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-06-30 15:31 ` [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing Shashi Mallela
2021-07-05 14:07 ` Peter Maydell
@ 2021-07-05 14:54 ` Peter Maydell
2021-07-06 0:47 ` shashi.mallela
2021-07-06 10:05 ` Eric Auger
2 siblings, 1 reply; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 14:54 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>
> Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
> translation which triggers an LPI via INT command as well as write
> to GITS_TRANSLATER register,defined enum to differentiate between ITS
> command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
> Each of these commands make use of other functionalities implemented to
> get device table entry,collection table entry or interrupt translation
> table entry required for their processing.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> ---
> +static MemTxResult process_mapti(GICv3ITSState *s, uint64_t value,
> + uint32_t offset, bool ignore_pInt)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint32_t devid, eventid;
> + uint32_t pIntid = 0;
> + uint32_t max_eventid, max_Intid;
> + bool dte_valid;
> + MemTxResult res = MEMTX_OK;
> + uint16_t icid = 0;
> + uint64_t dte = 0;
> + IteEntry ite;
> + uint32_t int_spurious = INTID_SPURIOUS;
> + uint64_t idbits;
> +
> + devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + eventid = (value & EVENTID_MASK);
> +
> + if (!ignore_pInt) {
> + pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT);
> + }
> +
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + icid = value & ICID_MASK;
> +
> + dte = get_dte(s, devid, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> + dte_valid = dte & TABLE_ENTRY_VALID_MASK;
> +
> + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> +
> + if (!ignore_pInt) {
> + idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser, GICR_PROPBASER,
> + IDBITS), GICD_TYPER_IDBITS);
I missed this the first time around, but I don't think this is right.
Different CPUs could have different GICR_PROPBASER values, so checking
against just one of them is wrong. The pseudocode only tests LPIOutOfRange()
which is documented as testing "larger than GICD_TYPER.IDbits or not in
the LPI range and not 1023". So I don't think we should be looking
at the GICR_PROPBASER field here.
More generally, "s->gicv3->cpu->something" is usually going to be
wrong, because it is implicitly looking at CPU 0; often either there
should be something else telling is which CPU to use (as in
&s->gicv3->cpu[rdbase] where the CTE told us which redistributor),
or we might need to operate on all CPUs/redistributors. The only
exception is where we can guarantee that all the CPUs are the same
(eg when looking at GICR_TYPER.PLPIS.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
2021-06-30 15:31 ` [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework Shashi Mallela
@ 2021-07-05 14:58 ` Peter Maydell
2021-07-05 15:55 ` shashi.mallela
2021-07-06 7:44 ` Eric Auger
1 sibling, 1 reply; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 14:58 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>
> Added register definitions relevant to ITS,implemented overall
> ITS device framework with stubs for ITS control and translater
> regions read/write,extended ITS common to handle mmio init between
> existing kvm device and newer qemu device.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> +static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
> +{
> + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> +
> + gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops);
> +
> + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
Can you remind me why we make this check, please? When would we
have created an ITS device but not have a GICv3 with LPI support?
Maybe it would be better to either
(a) simply create the ITS and assume that the board connected it up
to a GICv3 that supports it
(b) check every CPU for whether PLPIS is set, and if one of them does
not have it set then return an error from the ITS realize
?
(Found this by looking for code where we do s->gicv3->cpu->something...)
> + /* set the ITS default features supported */
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
> + GITS_TYPE_PHYSICAL);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE,
> + ITS_ITT_ENTRY_SIZE - 1);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS, ITS_IDBITS);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS, ITS_DEVBITS);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS, ITS_CIDBITS);
> + }
> +}
> +
> +static void gicv3_its_reset(DeviceState *dev)
> +{
> + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> + GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
> +
> + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
Similarly here.
> + c->parent_reset(dev);
> +
> + /* Quiescent bit reset to 1 */
> + s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
> +
> + /*
> + * setting GITS_BASER0.Type = 0b001 (Device)
> + * GITS_BASER1.Type = 0b100 (Collection Table)
> + * GITS_BASER<n>.Type,where n = 3 to 7 are 0b00 (Unimplemented)
> + * GITS_BASER<0,1>.Page_Size = 64KB
> + * and default translation table entry size to 16 bytes
> + */
> + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE,
> + GITS_ITT_TYPE_DEVICE);
> + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, PAGESIZE,
> + GITS_BASER_PAGESIZE_64K);
> + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, ENTRYSIZE,
> + GITS_DTE_SIZE - 1);
> +
> + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE,
> + GITS_ITT_TYPE_COLLECTION);
> + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, PAGESIZE,
> + GITS_BASER_PAGESIZE_64K);
> + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE,
> + GITS_CTE_SIZE - 1);
> + }
> +}
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC
2021-06-30 15:31 ` [PATCH v5 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela
@ 2021-07-05 14:59 ` Peter Maydell
0 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 14:59 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>
> Included creation of ITS as part of SBSA platform GIC
> initialization.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
This looks OK to me. Leif, are you happy with this patch now ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 10/10] tests/data/acpi/virt: Update IORT files for ITS
2021-06-30 15:31 ` [PATCH v5 10/10] tests/data/acpi/virt: Update IORT files for ITS Shashi Mallela
@ 2021-07-05 15:02 ` Peter Maydell
0 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 15:02 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>
> Updated expected IORT files applicable with latest GICv3
> ITS changes.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
The comment in tests/qtest/bios-tables-test.c requests that
patches with updates to the expected binaries should include
the IASL diffs in the commit message (so that reviewers can
confirm that the changes happening are sensible).
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 00/10] GICv3 LPI and ITS feature implementation
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
` (9 preceding siblings ...)
2021-06-30 15:31 ` [PATCH v5 10/10] tests/data/acpi/virt: Update IORT files for ITS Shashi Mallela
@ 2021-07-05 15:05 ` Peter Maydell
10 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 15:05 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
Eric Auger, qemu-arm, Igor Mammedov, Leif Lindholm
On Wed, 30 Jun 2021 at 16:31, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>
> This patchset implements qemu device model for enabling physical
> LPI support and ITS functionality in GIC as per GICv3 specification.
> Both flat table and 2 level tables are implemented.The ITS commands
> for adding/deleting ITS table entries,trigerring LPI interrupts are
> implemented.Translated LPI interrupt ids are processed by redistributor
> to determine priority and set pending state appropriately before
> forwarding the same to cpu interface.
> The ITS feature support has been added to sbsa-ref platform as well as
> virt platform,wherein the emulated functionality co-exists with kvm
> kernel functionality.
>
> Changes in v5:
> - v4 review comments addressed
> - All kvm_unit_tests PASS
You forgot to CC Eric.
Anyway, I've now reviewed v5.
This is now getting pretty tight to get into 6.1 -- a v6 would have
to be on list and reviewed by the end of the week at the latest.
I think we might have to slip this to 6.2, I'm afraid.
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
2021-07-05 14:58 ` Peter Maydell
@ 2021-07-05 15:55 ` shashi.mallela
2021-07-05 16:25 ` Peter Maydell
0 siblings, 1 reply; 41+ messages in thread
From: shashi.mallela @ 2021-07-05 15:55 UTC (permalink / raw)
To: Peter Maydell
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> shashi.mallela@linaro.org> wrote:
> > Added register definitions relevant to ITS,implemented overall
> > ITS device framework with stubs for ITS control and translater
> > regions read/write,extended ITS common to handle mmio init between
> > existing kvm device and newer qemu device.
> >
> > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> > +static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
> > +{
> > + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > +
> > + gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > &gicv3_its_translation_ops);
> > +
> > + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
>
> Can you remind me why we make this check, please? When would we
> have created an ITS device but not have a GICv3 with LPI support?
This check applies to GIC's physical LPI support only as against GIC's
virtual LPI support.
>
> Maybe it would be better to either
> (a) simply create the ITS and assume that the board connected it up
> to a GICv3 that supports it
> (b) check every CPU for whether PLPIS is set, and if one of them does
> not have it set then return an error from the ITS realize
>
> ?
>
> (Found this by looking for code where we do s->gicv3->cpu-
> >something...)
>
> > + /* set the ITS default features supported */
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
> > + GITS_TYPE_PHYSICAL);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER,
> > ITT_ENTRY_SIZE,
> > + ITS_ITT_ENTRY_SIZE - 1);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS,
> > ITS_IDBITS);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS,
> > ITS_DEVBITS);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS,
> > ITS_CIDBITS);
> > + }
> > +}
> > +
> > +static void gicv3_its_reset(DeviceState *dev)
> > +{
> > + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > + GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
> > +
> > + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
>
> Similarly here.
>
> > + c->parent_reset(dev);
> > +
> > + /* Quiescent bit reset to 1 */
> > + s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
> > +
> > + /*
> > + * setting GITS_BASER0.Type = 0b001 (Device)
> > + * GITS_BASER1.Type = 0b100 (Collection Table)
> > + * GITS_BASER<n>.Type,where n = 3 to 7 are 0b00
> > (Unimplemented)
> > + * GITS_BASER<0,1>.Page_Size = 64KB
> > + * and default translation table entry size to 16 bytes
> > + */
> > + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE,
> > + GITS_ITT_TYPE_DEVICE);
> > + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER,
> > PAGESIZE,
> > + GITS_BASER_PAGESIZE_64K);
> > + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER,
> > ENTRYSIZE,
> > + GITS_DTE_SIZE - 1);
> > +
> > + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE,
> > + GITS_ITT_TYPE_COLLECTION);
> > + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER,
> > PAGESIZE,
> > + GITS_BASER_PAGESIZE_64K);
> > + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER,
> > ENTRYSIZE,
> > + GITS_CTE_SIZE - 1);
> > + }
> > +}
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
2021-07-05 15:55 ` shashi.mallela
@ 2021-07-05 16:25 ` Peter Maydell
2021-07-05 17:04 ` shashi.mallela
0 siblings, 1 reply; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 16:25 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Mon, 5 Jul 2021 at 16:55, <shashi.mallela@linaro.org> wrote:
>
> On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > shashi.mallela@linaro.org> wrote:
> > > Added register definitions relevant to ITS,implemented overall
> > > ITS device framework with stubs for ITS control and translater
> > > regions read/write,extended ITS common to handle mmio init between
> > > existing kvm device and newer qemu device.
> > >
> > > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> > > +static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
> > > +{
> > > + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > > +
> > > + gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > > &gicv3_its_translation_ops);
> > > +
> > > + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> >
> > Can you remind me why we make this check, please? When would we
> > have created an ITS device but not have a GICv3 with LPI support?
> This check applies to GIC's physical LPI support only as against GIC's
> virtual LPI support.
Right, but when would we have a GIC with no physical LPI support
but an ITS is present ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
2021-07-05 16:25 ` Peter Maydell
@ 2021-07-05 17:04 ` shashi.mallela
2021-07-05 18:58 ` Peter Maydell
0 siblings, 1 reply; 41+ messages in thread
From: shashi.mallela @ 2021-07-05 17:04 UTC (permalink / raw)
To: Peter Maydell
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Mon, 2021-07-05 at 17:25 +0100, Peter Maydell wrote:
> On Mon, 5 Jul 2021 at 16:55, <shashi.mallela@linaro.org> wrote:
> > On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > > shashi.mallela@linaro.org> wrote:
> > > > Added register definitions relevant to ITS,implemented overall
> > > > ITS device framework with stubs for ITS control and translater
> > > > regions read/write,extended ITS common to handle mmio init
> > > > between
> > > > existing kvm device and newer qemu device.
> > > >
> > > > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> > > > +static void gicv3_arm_its_realize(DeviceState *dev, Error
> > > > **errp)
> > > > +{
> > > > + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > > > +
> > > > + gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > > > &gicv3_its_translation_ops);
> > > > +
> > > > + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> > >
> > > Can you remind me why we make this check, please? When would we
> > > have created an ITS device but not have a GICv3 with LPI support?
> > This check applies to GIC's physical LPI support only as against
> > GIC's
> > virtual LPI support.
>
> Right, but when would we have a GIC with no physical LPI support
> but an ITS is present ?
If we only support Direct injection of virtual interrupts (which can
have their own vPEID and the vPE table),then the ITS present could havejust virtual LPI support
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
2021-07-05 17:04 ` shashi.mallela
@ 2021-07-05 18:58 ` Peter Maydell
2021-07-07 2:08 ` shashi.mallela
0 siblings, 1 reply; 41+ messages in thread
From: Peter Maydell @ 2021-07-05 18:58 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Mon, 5 Jul 2021 at 18:04, <shashi.mallela@linaro.org> wrote:
>
> On Mon, 2021-07-05 at 17:25 +0100, Peter Maydell wrote:
> > On Mon, 5 Jul 2021 at 16:55, <shashi.mallela@linaro.org> wrote:
> > > On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> > > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > > > shashi.mallela@linaro.org> wrote:
> > > > > Added register definitions relevant to ITS,implemented overall
> > > > > ITS device framework with stubs for ITS control and translater
> > > > > regions read/write,extended ITS common to handle mmio init
> > > > > between
> > > > > existing kvm device and newer qemu device.
> > > > >
> > > > > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > > > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> > > > > +static void gicv3_arm_its_realize(DeviceState *dev, Error
> > > > > **errp)
> > > > > +{
> > > > > + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > > > > +
> > > > > + gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > > > > &gicv3_its_translation_ops);
> > > > > +
> > > > > + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> > > >
> > > > Can you remind me why we make this check, please? When would we
> > > > have created an ITS device but not have a GICv3 with LPI support?
> > > This check applies to GIC's physical LPI support only as against
> > > GIC's
> > > virtual LPI support.
> >
> > Right, but when would we have a GIC with no physical LPI support
> > but an ITS is present ?
> If we only support Direct injection of virtual interrupts (which can
> have their own vPEID and the vPE table),then the ITS present could havejust virtual LPI support
This patchset does not support a virtual-LPI-only ITS, though:
it doesn't support virtual LPIs at all.
If you use it with CPUs without physical LPI support , this code will skip
entirely setting GITS_TYPER and will make reset do nothing, and then the
rest of the ITS implementation will misbehave.
I think what we should do is:
* in realize, check every CPU to make sure its redistributor
supports physical LPIs, and return an error from realize if not
* in reset, don't check anything
If we add virtual-LPI-only ITS support later, we can always update
this code appropriately.
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-05 14:54 ` Peter Maydell
@ 2021-07-06 0:47 ` shashi.mallela
2021-07-06 3:25 ` shashi.mallela
0 siblings, 1 reply; 41+ messages in thread
From: shashi.mallela @ 2021-07-06 0:47 UTC (permalink / raw)
To: Peter Maydell
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> shashi.mallela@linaro.org> wrote:
> > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > ITS
> > translation which triggers an LPI via INT command as well as write
> > to GITS_TRANSLATER register,defined enum to differentiate between
> > ITS
> > command interrupt trigger and GITS_TRANSLATER based interrupt
> > trigger.
> > Each of these commands make use of other functionalities
> > implemented to
> > get device table entry,collection table entry or interrupt
> > translation
> > table entry required for their processing.
> >
> > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > ---
> > +static MemTxResult process_mapti(GICv3ITSState *s, uint64_t value,
> > + uint32_t offset, bool
> > ignore_pInt)
> > +{
> > + AddressSpace *as = &s->gicv3->dma_as;
> > + uint32_t devid, eventid;
> > + uint32_t pIntid = 0;
> > + uint32_t max_eventid, max_Intid;
> > + bool dte_valid;
> > + MemTxResult res = MEMTX_OK;
> > + uint16_t icid = 0;
> > + uint64_t dte = 0;
> > + IteEntry ite;
> > + uint32_t int_spurious = INTID_SPURIOUS;
> > + uint64_t idbits;
> > +
> > + devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> > + offset += NUM_BYTES_IN_DW;
> > + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > + MEMTXATTRS_UNSPECIFIED, &res);
> > +
> > + if (res != MEMTX_OK) {
> > + return res;
> > + }
> > +
> > + eventid = (value & EVENTID_MASK);
> > +
> > + if (!ignore_pInt) {
> > + pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT);
> > + }
> > +
> > + offset += NUM_BYTES_IN_DW;
> > + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > + MEMTXATTRS_UNSPECIFIED, &res);
> > +
> > + if (res != MEMTX_OK) {
> > + return res;
> > + }
> > +
> > + icid = value & ICID_MASK;
> > +
> > + dte = get_dte(s, devid, &res);
> > +
> > + if (res != MEMTX_OK) {
> > + return res;
> > + }
> > + dte_valid = dte & TABLE_ENTRY_VALID_MASK;
> > +
> > + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> > +
> > + if (!ignore_pInt) {
> > + idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser,
> > GICR_PROPBASER,
> > + IDBITS), GICD_TYPER_IDBITS);
>
> I missed this the first time around, but I don't think this is right.
> Different CPUs could have different GICR_PROPBASER values, so
> checking
> against just one of them is wrong. The pseudocode only tests
> LPIOutOfRange()
> which is documented as testing "larger than GICD_TYPER.IDbits or not
> in
> the LPI range and not 1023". So I don't think we should be looking
> at the GICR_PROPBASER field here.
>
> More generally, "s->gicv3->cpu->something" is usually going to be
> wrong, because it is implicitly looking at CPU 0; often either there
> should be something else telling is which CPU to use (as in
> &s->gicv3->cpu[rdbase] where the CTE told us which redistributor),
> or we might need to operate on all CPUs/redistributors. The only
> exception is where we can guarantee that all the CPUs are the same
> (eg when looking at GICR_TYPER.PLPIS.)
In that case,the validation of IDBITS(in case of ITS enabled) could be
done during the write of gicr_propbaser register value itself(in
arm_gicv3_redist.c) and the its command processing code here can just
extract the idbits for its use.
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-06 0:47 ` shashi.mallela
@ 2021-07-06 3:25 ` shashi.mallela
2021-07-06 9:19 ` Peter Maydell
2021-07-06 10:04 ` Eric Auger
0 siblings, 2 replies; 41+ messages in thread
From: shashi.mallela @ 2021-07-06 3:25 UTC (permalink / raw)
To: Peter Maydell
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Mon, 2021-07-05 at 20:47 -0400, shashi.mallela@linaro.org wrote:
> On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > shashi.mallela@linaro.org> wrote:
> > > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > > ITS
> > > translation which triggers an LPI via INT command as well as
> > > write
> > > to GITS_TRANSLATER register,defined enum to differentiate between
> > > ITS
> > > command interrupt trigger and GITS_TRANSLATER based interrupt
> > > trigger.
> > > Each of these commands make use of other functionalities
> > > implemented to
> > > get device table entry,collection table entry or interrupt
> > > translation
> > > table entry required for their processing.
> > >
> > > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > > ---
> > > +static MemTxResult process_mapti(GICv3ITSState *s, uint64_t
> > > value,
> > > + uint32_t offset, bool
> > > ignore_pInt)
> > > +{
> > > + AddressSpace *as = &s->gicv3->dma_as;
> > > + uint32_t devid, eventid;
> > > + uint32_t pIntid = 0;
> > > + uint32_t max_eventid, max_Intid;
> > > + bool dte_valid;
> > > + MemTxResult res = MEMTX_OK;
> > > + uint16_t icid = 0;
> > > + uint64_t dte = 0;
> > > + IteEntry ite;
> > > + uint32_t int_spurious = INTID_SPURIOUS;
> > > + uint64_t idbits;
> > > +
> > > + devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> > > + offset += NUM_BYTES_IN_DW;
> > > + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > > + MEMTXATTRS_UNSPECIFIED, &res);
> > > +
> > > + if (res != MEMTX_OK) {
> > > + return res;
> > > + }
> > > +
> > > + eventid = (value & EVENTID_MASK);
> > > +
> > > + if (!ignore_pInt) {
> > > + pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT);
> > > + }
> > > +
> > > + offset += NUM_BYTES_IN_DW;
> > > + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > > + MEMTXATTRS_UNSPECIFIED, &res);
> > > +
> > > + if (res != MEMTX_OK) {
> > > + return res;
> > > + }
> > > +
> > > + icid = value & ICID_MASK;
> > > +
> > > + dte = get_dte(s, devid, &res);
> > > +
> > > + if (res != MEMTX_OK) {
> > > + return res;
> > > + }
> > > + dte_valid = dte & TABLE_ENTRY_VALID_MASK;
> > > +
> > > + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> > > +
> > > + if (!ignore_pInt) {
> > > + idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser,
> > > GICR_PROPBASER,
> > > + IDBITS), GICD_TYPER_IDBITS);
> >
> > I missed this the first time around, but I don't think this is
> > right.
> > Different CPUs could have different GICR_PROPBASER values, so
> > checking
> > against just one of them is wrong. The pseudocode only tests
> > LPIOutOfRange()
> > which is documented as testing "larger than GICD_TYPER.IDbits or
> > not
> > in
> > the LPI range and not 1023". So I don't think we should be looking
> > at the GICR_PROPBASER field here.
> >
> > More generally, "s->gicv3->cpu->something" is usually going to be
> > wrong, because it is implicitly looking at CPU 0; often either
> > there
> > should be something else telling is which CPU to use (as in
> > &s->gicv3->cpu[rdbase] where the CTE told us which redistributor),
> > or we might need to operate on all CPUs/redistributors. The only
> > exception is where we can guarantee that all the CPUs are the same
> > (eg when looking at GICR_TYPER.PLPIS.)
> In that case,the validation of IDBITS(in case of ITS enabled) could
> be
> done during the write of gicr_propbaser register value itself(in
> arm_gicv3_redist.c) and the its command processing code here can just
> extract the idbits for its use.
> > thanks
> > -- PMM
Hi Peter
Please ignore my last comment.
To address this scenario,i think the feasible option would be to call
get_cte() to get the rdbase corresponding to icid value passed to mapti
command.Since each icid is mapped to a rdbase(by virtue of calling MAPC
command),if the collection table has a valid mapping for this icid we
continue processing this MAPTI command using &s->gicv3->cpu[rdbase]
applicable propbaser value to validate idbits, else return without
further processing.
Thanks
Shashi
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
2021-06-30 15:31 ` [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework Shashi Mallela
2021-07-05 14:58 ` Peter Maydell
@ 2021-07-06 7:44 ` Eric Auger
2021-07-07 2:06 ` shashi.mallela
1 sibling, 1 reply; 41+ messages in thread
From: Eric Auger @ 2021-07-06 7:44 UTC (permalink / raw)
To: Shashi Mallela, peter.maydell, leif, rad, mst, imammedo
Cc: qemu-arm, qemu-devel
Hi,
On 6/30/21 5:31 PM, Shashi Mallela wrote:
> Added register definitions relevant to ITS,implemented overall
> ITS device framework with stubs for ITS control and translater
> regions read/write,extended ITS common to handle mmio init between
> existing kvm device and newer qemu device.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Some of my comments in v4 were not commented nor addressed in v5.
Also here and in the other respinned patches, please add an individual
history log to track the major changes you made from n-1 to n to help
the review.
Thanks
Eric
> ---
> hw/intc/arm_gicv3_its.c | 240 +++++++++++++++++++++++++
> hw/intc/arm_gicv3_its_common.c | 7 +-
> hw/intc/arm_gicv3_its_kvm.c | 2 +-
> hw/intc/gicv3_internal.h | 88 +++++++--
> hw/intc/meson.build | 1 +
> include/hw/intc/arm_gicv3_its_common.h | 9 +-
> 6 files changed, 331 insertions(+), 16 deletions(-)
> create mode 100644 hw/intc/arm_gicv3_its.c
>
> diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> new file mode 100644
> index 0000000000..545cda3665
> --- /dev/null
> +++ b/hw/intc/arm_gicv3_its.c
> @@ -0,0 +1,240 @@
> +/*
> + * ITS emulation for a GICv3-based system
> + *
> + * Copyright Linaro.org 2021
> + *
> + * Authors:
> + * Shashi Mallela <shashi.mallela@linaro.org>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or (at your
> + * option) any later version. See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/intc/arm_gicv3_its_common.h"
> +#include "gicv3_internal.h"
> +#include "qom/object.h"
> +
> +typedef struct GICv3ITSClass GICv3ITSClass;
> +/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
> +DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
> + ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
> +
> +struct GICv3ITSClass {
> + GICv3ITSCommonClass parent_class;
> + void (*parent_reset)(DeviceState *dev);
> +};
> +
> +static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
> + uint64_t data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + MemTxResult result = MEMTX_OK;
> +
> + return result;
> +}
> +
> +static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
> + uint64_t value, MemTxAttrs attrs)
> +{
> + MemTxResult result = MEMTX_OK;
> +
> + return result;
> +}
> +
> +static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
> + uint64_t *data, MemTxAttrs attrs)
> +{
> + MemTxResult result = MEMTX_OK;
> +
> + return result;
> +}
> +
> +static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
> + uint64_t value, MemTxAttrs attrs)
> +{
> + MemTxResult result = MEMTX_OK;
> +
> + return result;
> +}
> +
> +static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
> + uint64_t *data, MemTxAttrs attrs)
> +{
> + MemTxResult result = MEMTX_OK;
> +
> + return result;
> +}
> +
> +static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
> + unsigned size, MemTxAttrs attrs)
> +{
> + GICv3ITSState *s = (GICv3ITSState *)opaque;
> + MemTxResult result;
> +
> + switch (size) {
> + case 4:
> + result = its_readl(s, offset, data, attrs);
> + break;
> + case 8:
> + result = its_readll(s, offset, data, attrs);
> + break;
> + default:
> + result = MEMTX_ERROR;
> + break;
> + }
> +
> + if (result == MEMTX_ERROR) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid guest read at offset " TARGET_FMT_plx
> + "size %u\n", __func__, offset, size);
> + /*
> + * The spec requires that reserved registers are RAZ/WI;
> + * so use MEMTX_ERROR returns from leaf functions as a way to
> + * trigger the guest-error logging but don't return it to
> + * the caller, or we'll cause a spurious guest data abort.
> + */
> + result = MEMTX_OK;
> + *data = 0;
> + }
> + return result;
> +}
> +
> +static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
> + unsigned size, MemTxAttrs attrs)
> +{
> + GICv3ITSState *s = (GICv3ITSState *)opaque;
> + MemTxResult result;
> +
> + switch (size) {
> + case 4:
> + result = its_writel(s, offset, data, attrs);
> + break;
> + case 8:
> + result = its_writell(s, offset, data, attrs);
> + break;
> + default:
> + result = MEMTX_ERROR;
> + break;
> + }
> +
> + if (result == MEMTX_ERROR) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid guest write at offset " TARGET_FMT_plx
> + "size %u\n", __func__, offset, size);
> + /*
> + * The spec requires that reserved registers are RAZ/WI;
> + * so use MEMTX_ERROR returns from leaf functions as a way to
> + * trigger the guest-error logging but don't return it to
> + * the caller, or we'll cause a spurious guest data abort.
> + */
> + result = MEMTX_OK;
> + }
> + return result;
> +}
> +
> +static const MemoryRegionOps gicv3_its_control_ops = {
> + .read_with_attrs = gicv3_its_read,
> + .write_with_attrs = gicv3_its_write,
> + .valid.min_access_size = 4,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 4,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static const MemoryRegionOps gicv3_its_translation_ops = {
> + .write_with_attrs = gicv3_its_translation_write,
> + .valid.min_access_size = 2,
> + .valid.max_access_size = 4,
> + .impl.min_access_size = 2,
> + .impl.max_access_size = 4,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
> +{
> + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> +
> + gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops);
> +
> + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> + /* set the ITS default features supported */
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
> + GITS_TYPE_PHYSICAL);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE,
> + ITS_ITT_ENTRY_SIZE - 1);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS, ITS_IDBITS);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS, ITS_DEVBITS);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1);
> + s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS, ITS_CIDBITS);
> + }
> +}
> +
> +static void gicv3_its_reset(DeviceState *dev)
> +{
> + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> + GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
> +
> + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> + c->parent_reset(dev);
> +
> + /* Quiescent bit reset to 1 */
> + s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
> +
> + /*
> + * setting GITS_BASER0.Type = 0b001 (Device)
> + * GITS_BASER1.Type = 0b100 (Collection Table)
> + * GITS_BASER<n>.Type,where n = 3 to 7 are 0b00 (Unimplemented)
> + * GITS_BASER<0,1>.Page_Size = 64KB
> + * and default translation table entry size to 16 bytes
> + */
> + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE,
> + GITS_ITT_TYPE_DEVICE);
> + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, PAGESIZE,
> + GITS_BASER_PAGESIZE_64K);
> + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, ENTRYSIZE,
> + GITS_DTE_SIZE - 1);
> +
> + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE,
> + GITS_ITT_TYPE_COLLECTION);
> + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, PAGESIZE,
> + GITS_BASER_PAGESIZE_64K);
> + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE,
> + GITS_CTE_SIZE - 1);
> + }
> +}
> +
> +static Property gicv3_its_props[] = {
> + DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3",
> + GICv3State *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void gicv3_its_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
> +
> + dc->realize = gicv3_arm_its_realize;
> + device_class_set_props(dc, gicv3_its_props);
> + device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
> +}
> +
> +static const TypeInfo gicv3_its_info = {
> + .name = TYPE_ARM_GICV3_ITS,
> + .parent = TYPE_ARM_GICV3_ITS_COMMON,
> + .instance_size = sizeof(GICv3ITSState),
> + .class_init = gicv3_its_class_init,
> + .class_size = sizeof(GICv3ITSClass),
> +};
> +
> +static void gicv3_its_register_types(void)
> +{
> + type_register_static(&gicv3_its_info);
> +}
> +
> +type_init(gicv3_its_register_types)
> diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
> index 66c4c6a188..7d7f3882e7 100644
> --- a/hw/intc/arm_gicv3_its_common.c
> +++ b/hw/intc/arm_gicv3_its_common.c
> @@ -50,6 +50,8 @@ static int gicv3_its_post_load(void *opaque, int version_id)
>
> static const VMStateDescription vmstate_its = {
> .name = "arm_gicv3_its",
> + .version_id = 1,
> + .minimum_version_id = 1,
> .pre_save = gicv3_its_pre_save,
> .post_load = gicv3_its_post_load,
> .priority = MIG_PRI_GICV3_ITS,
> @@ -99,14 +101,15 @@ static const MemoryRegionOps gicv3_its_trans_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
> +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
> + const MemoryRegionOps *tops)
> {
> SysBusDevice *sbd = SYS_BUS_DEVICE(s);
>
> memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
> "control", ITS_CONTROL_SIZE);
> memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
> - &gicv3_its_trans_ops, s,
> + tops ? tops : &gicv3_its_trans_ops, s,
> "translation", ITS_TRANS_SIZE);
>
> /* Our two regions are always adjacent, therefore we now combine them
> diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
> index b554d2ede0..0b4cbed28b 100644
> --- a/hw/intc/arm_gicv3_its_kvm.c
> +++ b/hw/intc/arm_gicv3_its_kvm.c
> @@ -106,7 +106,7 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
> kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
> KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0);
>
> - gicv3_its_init_mmio(s, NULL);
> + gicv3_its_init_mmio(s, NULL, NULL);
>
> if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
> GITS_CTLR)) {
> diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
> index 05303a55c8..e0b06930a7 100644
> --- a/hw/intc/gicv3_internal.h
> +++ b/hw/intc/gicv3_internal.h
> @@ -24,6 +24,7 @@
> #ifndef QEMU_ARM_GICV3_INTERNAL_H
> #define QEMU_ARM_GICV3_INTERNAL_H
>
> +#include "hw/registerfields.h"
> #include "hw/intc/arm_gicv3_common.h"
>
> /* Distributor registers, as offsets from the distributor base address */
> @@ -67,6 +68,9 @@
> #define GICD_CTLR_E1NWF (1U << 7)
> #define GICD_CTLR_RWP (1U << 31)
>
> +/* 16 bits EventId */
> +#define GICD_TYPER_IDBITS 0xf
> +
> /*
> * Redistributor frame offsets from RD_base
> */
> @@ -122,18 +126,6 @@
> #define GICR_WAKER_ProcessorSleep (1U << 1)
> #define GICR_WAKER_ChildrenAsleep (1U << 2)
>
> -#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
> -#define GICR_PROPBASER_ADDR_MASK (0xfffffffffULL << 12)
> -#define GICR_PROPBASER_SHAREABILITY_MASK (3U << 10)
> -#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
> -#define GICR_PROPBASER_IDBITS_MASK (0x1f)
> -
> -#define GICR_PENDBASER_PTZ (1ULL << 62)
> -#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
> -#define GICR_PENDBASER_ADDR_MASK (0xffffffffULL << 16)
> -#define GICR_PENDBASER_SHAREABILITY_MASK (3U << 10)
> -#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
> -
> #define ICC_CTLR_EL1_CBPR (1U << 0)
> #define ICC_CTLR_EL1_EOIMODE (1U << 1)
> #define ICC_CTLR_EL1_PMHE (1U << 6)
> @@ -239,6 +231,78 @@
> #define ICH_VTR_EL2_PREBITS_SHIFT 26
> #define ICH_VTR_EL2_PRIBITS_SHIFT 29
>
> +/* ITS Registers */
> +
> +FIELD(GITS_BASER, SIZE, 0, 8)
> +FIELD(GITS_BASER, PAGESIZE, 8, 2)
> +FIELD(GITS_BASER, SHAREABILITY, 10, 2)
> +FIELD(GITS_BASER, PHYADDR, 12, 36)
> +FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
> +FIELD(GITS_BASER, PHYADDRH_64K, 48, 4)
> +FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
> +FIELD(GITS_BASER, OUTERCACHE, 53, 3)
> +FIELD(GITS_BASER, TYPE, 56, 3)
> +FIELD(GITS_BASER, INNERCACHE, 59, 3)
> +FIELD(GITS_BASER, INDIRECT, 62, 1)
> +FIELD(GITS_BASER, VALID, 63, 1)
> +
> +FIELD(GITS_CTLR, QUIESCENT, 31, 1)
> +
> +FIELD(GITS_TYPER, PHYSICAL, 0, 1)
> +FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4)
> +FIELD(GITS_TYPER, IDBITS, 8, 5)
> +FIELD(GITS_TYPER, DEVBITS, 13, 5)
> +FIELD(GITS_TYPER, SEIS, 18, 1)
> +FIELD(GITS_TYPER, PTA, 19, 1)
> +FIELD(GITS_TYPER, CIDBITS, 32, 4)
> +FIELD(GITS_TYPER, CIL, 36, 1)
> +
> +#define GITS_BASER_PAGESIZE_4K 0
> +#define GITS_BASER_PAGESIZE_16K 1
> +#define GITS_BASER_PAGESIZE_64K 2
> +
> +#define GITS_ITT_TYPE_DEVICE 1ULL
> +#define GITS_ITT_TYPE_COLLECTION 4ULL
> +
> +/**
> + * Default features advertised by this version of ITS
> + */
> +/* Physical LPIs supported */
> +#define GITS_TYPE_PHYSICAL (1U << 0)
> +
> +/*
> + * 12 bytes Interrupt translation Table Entry size
> + * ITE Lower 8 Bytes
> + * Valid = 1 bit,InterruptType = 1 bit,
> + * Size of LPI number space[considering max 24 bits],
> + * Size of LPI number space[considering max 24 bits],
> + * ITE Higher 4 Bytes
> + * ICID = 16 bits,
> + * vPEID = 16 bits
> + */
> +#define ITS_ITT_ENTRY_SIZE 0xC
> +
> +/* 16 bits EventId */
> +#define ITS_IDBITS GICD_TYPER_IDBITS
> +
> +/* 16 bits DeviceId */
> +#define ITS_DEVBITS 0xF
> +
> +/* 16 bits CollectionId */
> +#define ITS_CIDBITS 0xF
> +
> +/*
> + * 8 bytes Device Table Entry size
> + * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits
> + */
> +#define GITS_DTE_SIZE (0x8ULL)
> +
> +/*
> + * 8 bytes Collection Table Entry size
> + * Valid = 1 bit,RDBase = 36 bits(considering max RDBASE)
> + */
> +#define GITS_CTE_SIZE (0x8ULL)
> +
> /* Special interrupt IDs */
> #define INTID_SECURE 1020
> #define INTID_NONSECURE 1021
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 6e52a166e3..4dcfea6aa8 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -8,6 +8,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
> 'arm_gicv3_dist.c',
> 'arm_gicv3_its_common.c',
> 'arm_gicv3_redist.c',
> + 'arm_gicv3_its.c',
> ))
> softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
> softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c'))
> diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
> index 5a0952b404..65d1191db1 100644
> --- a/include/hw/intc/arm_gicv3_its_common.h
> +++ b/include/hw/intc/arm_gicv3_its_common.h
> @@ -25,17 +25,22 @@
> #include "hw/intc/arm_gicv3_common.h"
> #include "qom/object.h"
>
> +#define TYPE_ARM_GICV3_ITS "arm-gicv3-its"
> +
> #define ITS_CONTROL_SIZE 0x10000
> #define ITS_TRANS_SIZE 0x10000
> #define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
>
> #define GITS_CTLR 0x0
> #define GITS_IIDR 0x4
> +#define GITS_TYPER 0x8
> #define GITS_CBASER 0x80
> #define GITS_CWRITER 0x88
> #define GITS_CREADR 0x90
> #define GITS_BASER 0x100
>
> +#define GITS_TRANSLATER 0x0040
> +
> struct GICv3ITSState {
> SysBusDevice parent_obj;
>
> @@ -52,6 +57,7 @@ struct GICv3ITSState {
> /* Registers */
> uint32_t ctlr;
> uint32_t iidr;
> + uint64_t typer;
> uint64_t cbaser;
> uint64_t cwriter;
> uint64_t creadr;
> @@ -62,7 +68,8 @@ struct GICv3ITSState {
>
> typedef struct GICv3ITSState GICv3ITSState;
>
> -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
> +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
> + const MemoryRegionOps *tops);
>
> #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
> typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-06 3:25 ` shashi.mallela
@ 2021-07-06 9:19 ` Peter Maydell
2021-07-06 12:46 ` shashi.mallela
2021-07-06 10:04 ` Eric Auger
1 sibling, 1 reply; 41+ messages in thread
From: Peter Maydell @ 2021-07-06 9:19 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Tue, 6 Jul 2021 at 04:25, <shashi.mallela@linaro.org> wrote:
>
> On Mon, 2021-07-05 at 20:47 -0400, shashi.mallela@linaro.org wrote:
> > On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> > > I missed this the first time around, but I don't think this is
> > > right.
> > > Different CPUs could have different GICR_PROPBASER values, so
> > > checking
> > > against just one of them is wrong. The pseudocode only tests
> > > LPIOutOfRange()
> > > which is documented as testing "larger than GICD_TYPER.IDbits or
> > > not
> > > in
> > > the LPI range and not 1023". So I don't think we should be looking
> > > at the GICR_PROPBASER field here.
> > >
> > > More generally, "s->gicv3->cpu->something" is usually going to be
> > > wrong, because it is implicitly looking at CPU 0; often either
> > > there
> > > should be something else telling is which CPU to use (as in
> > > &s->gicv3->cpu[rdbase] where the CTE told us which redistributor),
> > > or we might need to operate on all CPUs/redistributors. The only
> > > exception is where we can guarantee that all the CPUs are the same
> > > (eg when looking at GICR_TYPER.PLPIS.)
> Please ignore my last comment.
>
> To address this scenario,i think the feasible option would be to call
> get_cte() to get the rdbase corresponding to icid value passed to mapti
> command.Since each icid is mapped to a rdbase(by virtue of calling MAPC
> command),if the collection table has a valid mapping for this icid we
> continue processing this MAPTI command using &s->gicv3->cpu[rdbase]
> applicable propbaser value to validate idbits, else return without
> further processing.
But the pseudocode for MAPTI does not say anywhere that we should
be checking the pIntID against any CPU's GICR_PROPBASER field.
It is checked only by the checks in LPIOutOfRange(), which tests:
* is it larger than permitted by GICD_TYPER.IDbits
* is it not in the LPI range and not 1023
Checking whether the intID is too big and would cause us to index
off the end of the redistributor's configuration table should be done
later, only when the ITS actually sends the interrupt to a particular
redistributor, I think.
(You can't rely on the guest having done the MAPC before the MAPTI;
and in any case the guest could choose to do a MAPC to a different
redistributor after it's done the MAPTI.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-05 14:07 ` Peter Maydell
@ 2021-07-06 9:27 ` Eric Auger
2021-07-07 2:02 ` shashi.mallela
0 siblings, 1 reply; 41+ messages in thread
From: Eric Auger @ 2021-07-06 9:27 UTC (permalink / raw)
To: Peter Maydell, Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
Hi,
On 7/5/21 4:07 PM, Peter Maydell wrote:
> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>>
>> Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
>> translation which triggers an LPI via INT command as well as write
>> to GITS_TRANSLATER register,defined enum to differentiate between ITS
>> command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
>> Each of these commands make use of other functionalities implemented to
>> get device table entry,collection table entry or interrupt translation
>> table entry required for their processing.
>>
>> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
>> ---
>> hw/intc/arm_gicv3_its.c | 361 ++++++++++++++++++++++++++++-
>> hw/intc/gicv3_internal.h | 26 +++
>> include/hw/intc/arm_gicv3_common.h | 2 +
>> 3 files changed, 388 insertions(+), 1 deletion(-)
>
>> +/*
>> + * This function handles the processing of following commands based on
>> + * the ItsCmdType parameter passed:-
>> + * 1. trigerring of lpi interrupt translation via ITS INT command
>> + * 2. trigerring of lpi interrupt translation via gits_translater register
>> + * 3. handling of ITS CLEAR command
>> + * 4. handling of ITS DISCARD command
>> + */
>
> "triggering"
>
>> #define DEVID_SHIFT 32
>> #define DEVID_MASK MAKE_64BIT_MASK(32, 32)
>
>> @@ -347,6 +368,11 @@ FIELD(MAPC, RDBASE, 16, 32)
>> * vPEID = 16 bits
>> */
>> #define ITS_ITT_ENTRY_SIZE 0xC
>> +#define ITE_ENTRY_INTTYPE_SHIFT 1
>> +#define ITE_ENTRY_INTID_SHIFT 2
>> +#define ITE_ENTRY_INTID_MASK ((1ULL << 24) - 1)
>> +#define ITE_ENTRY_INTSP_SHIFT 26
>> +#define ITE_ENTRY_ICID_MASK ((1ULL << 16) - 1)
>
> This is still using a MASK value that's at the bottom of the
> integer, not in its shifted location.
There are other locations, pointed out by former comments, where this
kind of unusual masking scheme is used but well...
Thanks
Eric
>
> Otherwise
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added
2021-06-30 15:31 ` [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added Shashi Mallela
@ 2021-07-06 9:29 ` Eric Auger
2021-07-08 17:27 ` Eric Auger
0 siblings, 1 reply; 41+ messages in thread
From: Eric Auger @ 2021-07-06 9:29 UTC (permalink / raw)
To: Shashi Mallela, peter.maydell, leif, rad, mst, imammedo
Cc: qemu-arm, qemu-devel
Hi,
On 6/30/21 5:31 PM, Shashi Mallela wrote:
> Defined descriptors for ITS device table,collection table and ITS
> command queue entities.Implemented register read/write functions,
> extract ITS table parameters and command queue parameters,extended
> gicv3 common to capture qemu address space(which host the ITS table
> platform memories required for subsequent ITS processing) and
> initialize the same in ITS device.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/intc/arm_gicv3_its.c | 376 +++++++++++++++++++++++++
> hw/intc/gicv3_internal.h | 31 +-
> include/hw/intc/arm_gicv3_common.h | 3 +
> include/hw/intc/arm_gicv3_its_common.h | 23 ++
> 4 files changed, 432 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> index 545cda3665..2d786a1e21 100644
> --- a/hw/intc/arm_gicv3_its.c
> +++ b/hw/intc/arm_gicv3_its.c
> @@ -28,6 +28,160 @@ struct GICv3ITSClass {
> void (*parent_reset)(DeviceState *dev);
> };
>
> +static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
> +{
> + uint64_t result = 0;
> +
> + switch (page_sz) {
> + case GITS_PAGE_SIZE_4K:
> + case GITS_PAGE_SIZE_16K:
> + result = FIELD_EX64(value, GITS_BASER, PHYADDR);
<< 12 ?
> + break;
> +
> + case GITS_PAGE_SIZE_64K:
> + result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16;
> + result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48;
> + break;
> +
> + default:
> + break;
> + }
> + return result;
> +}
> +
> +/*
> + * This function extracts the ITS Device and Collection table specific
> + * parameters (like base_addr, size etc) from GITS_BASER register.
> + * It is called during ITS enable and also during post_load migration
> + */
> +static void extract_table_params(GICv3ITSState *s)
> +{
> + uint16_t num_pages = 0;
> + uint8_t page_sz_type;
> + uint8_t type;
> + uint32_t page_sz = 0;
> + uint64_t value;
> +
> + for (int i = 0; i < 8; i++) {
> + value = s->baser[i];
> +
> + if (!value) {
> + continue;
> + }
> +
> + page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
> +
> + switch (page_sz_type) {
> + case 0:
> + page_sz = GITS_PAGE_SIZE_4K;
> + break;
> +
> + case 1:
> + page_sz = GITS_PAGE_SIZE_16K;
> + break;
> +
> + case 2:
> + case 3:
> + page_sz = GITS_PAGE_SIZE_64K;
> + break;
> +
> + default:
> + g_assert_not_reached();
> + }
> +
> + num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
> +
> + type = FIELD_EX64(value, GITS_BASER, TYPE);
> +
> + switch (type) {
> +
> + case GITS_ITT_TYPE_DEVICE:
> + memset(&s->dt, 0 , sizeof(s->dt));
> + s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
> +
> + if (!s->dt.valid) {
> + return;
> + }
> +
> + s->dt.page_sz = page_sz;
> + s->dt.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
> + s->dt.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
> +
> + if (!s->dt.indirect) {
> + s->dt.max_entries = (num_pages * page_sz) / s->dt.entry_sz;
> + } else {
> + s->dt.max_entries = (((num_pages * page_sz) /
> + L1TABLE_ENTRY_SIZE) *
> + (page_sz / s->dt.entry_sz));
> + }
> +
> + s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s->typer, GITS_TYPER,
> + DEVBITS) + 1));
> +
> + s->dt.base_addr = baser_base_addr(value, page_sz);
> +
> + break;
> +
> + case GITS_ITT_TYPE_COLLECTION:
> + memset(&s->ct, 0 , sizeof(s->ct));
> + s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
> +
> + /*
> + * GITS_TYPER.HCC is 0 for this implementation
> + * hence writes are discarded if ct.valid is 0
> + */
> + if (!s->ct.valid) {
> + return;
> + }
> +
> + s->ct.page_sz = page_sz;
> + s->ct.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
> + s->ct.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
> +
> + if (!s->ct.indirect) {
> + s->ct.max_entries = (num_pages * page_sz) / s->ct.entry_sz;
> + } else {
> + s->ct.max_entries = (((num_pages * page_sz) /
> + L1TABLE_ENTRY_SIZE) *
> + (page_sz / s->ct.entry_sz));
> + }
> +
> + if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
> + s->ct.maxids.max_collids = (1UL << (FIELD_EX64(s->typer,
> + GITS_TYPER, CIDBITS) + 1));
> + } else {
> + /* 16-bit CollectionId supported when CIL == 0 */
> + s->ct.maxids.max_collids = (1UL << 16);
> + }
> +
> + s->ct.base_addr = baser_base_addr(value, page_sz);
> +
> + break;
> +
> + default:
> + break;
> + }
> + }
> +}
> +
> +static void extract_cmdq_params(GICv3ITSState *s)
> +{
> + uint16_t num_pages = 0;
> + uint64_t value = s->cbaser;
> +
> + num_pages = FIELD_EX64(value, GITS_CBASER, SIZE) + 1;
> +
> + memset(&s->cq, 0 , sizeof(s->cq));
> + s->cq.valid = FIELD_EX64(value, GITS_CBASER, VALID);
> +
> + if (s->cq.valid) {
> + s->cq.max_entries = (num_pages * GITS_PAGE_SIZE_4K) /
> + GITS_CMDQ_ENTRY_SIZE;
> + s->cq.base_addr = FIELD_EX64(value, GITS_CBASER, PHYADDR);
> + s->cq.base_addr <<= R_GITS_CBASER_PHYADDR_SHIFT;
> + }
> +}
> +
> static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
> uint64_t data, unsigned size,
> MemTxAttrs attrs)
> @@ -41,7 +195,99 @@ static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
> uint64_t value, MemTxAttrs attrs)
> {
> MemTxResult result = MEMTX_OK;
> + int index;
>
> + switch (offset) {
> + case GITS_CTLR:
> + s->ctlr |= (value & ~(s->ctlr));
> +
> + if (s->ctlr & ITS_CTLR_ENABLED) {
> + extract_table_params(s);
> + extract_cmdq_params(s);
> + s->creadr = 0;
> + }
> + break;
> + case GITS_CBASER:
> + /*
> + * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
> + * already enabled
> + */
> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> + s->cbaser = deposit64(s->cbaser, 0, 32, value);
> + s->creadr = 0;
> + s->cwriter = s->creadr;
> + }
> + break;
> + case GITS_CBASER + 4:
> + /*
> + * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
> + * already enabled
> + */
> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> + s->cbaser = deposit64(s->cbaser, 32, 32, value);
> + s->creadr = 0;
> + s->cwriter = s->creadr;
> + }
> + break;
> + case GITS_CWRITER:
> + s->cwriter = deposit64(s->cwriter, 0, 32,
> + (value & ~R_GITS_CWRITER_RETRY_MASK));
> + break;
> + case GITS_CWRITER + 4:
> + s->cwriter = deposit64(s->cwriter, 32, 32, value);
> + break;
> + case GITS_CREADR:
> + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
> + s->creadr = deposit64(s->creadr, 0, 32,
> + (value & ~R_GITS_CREADR_STALLED_MASK));
> + } else {
> + /* RO register, ignore the write */
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid guest write to RO register at offset "
> + TARGET_FMT_plx "\n", __func__, offset);
> + }
> + break;
> + case GITS_CREADR + 4:
> + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
> + s->creadr = deposit64(s->creadr, 32, 32, value);
> + } else {
> + /* RO register, ignore the write */
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid guest write to RO register at offset "
> + TARGET_FMT_plx "\n", __func__, offset);
> + }
> + break;
> + case GITS_BASER ... GITS_BASER + 0x3f:
> + /*
> + * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is
> + * already enabled
> + */
> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> + index = (offset - GITS_BASER) / 8;
> +
> + if (offset & 7) {
> + value <<= 32;
> + value &= ~GITS_BASER_RO_MASK;
> + s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(0, 32);
> + s->baser[index] |= value;
> + } else {
> + value &= ~GITS_BASER_RO_MASK;
> + s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(32, 32);
> + s->baser[index] |= value;
> + }
> + }
> + break;
> + case GITS_IIDR:
> + case GITS_IDREGS ... GITS_IDREGS + 0x2f:
> + /* RO registers, ignore the write */
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid guest write to RO register at offset "
> + TARGET_FMT_plx "\n", __func__, offset);
> + break;
> + default:
> + result = MEMTX_ERROR;
> + break;
> + }
> return result;
> }
>
> @@ -49,7 +295,55 @@ static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
> uint64_t *data, MemTxAttrs attrs)
> {
> MemTxResult result = MEMTX_OK;
> + int index;
>
> + switch (offset) {
> + case GITS_CTLR:
> + *data = s->ctlr;
> + break;
> + case GITS_IIDR:
> + *data = gicv3_iidr();
> + break;
> + case GITS_IDREGS ... GITS_IDREGS + 0x2f:
> + /* ID registers */
> + *data = gicv3_idreg(offset - GITS_IDREGS);
> + break;
> + case GITS_TYPER:
> + *data = extract64(s->typer, 0, 32);
> + break;
> + case GITS_TYPER + 4:
> + *data = extract64(s->typer, 32, 32);
> + break;
> + case GITS_CBASER:
> + *data = extract64(s->cbaser, 0, 32);
> + break;
> + case GITS_CBASER + 4:
> + *data = extract64(s->cbaser, 32, 32);
> + break;
> + case GITS_CREADR:
> + *data = extract64(s->creadr, 0, 32);
> + break;
> + case GITS_CREADR + 4:
> + *data = extract64(s->creadr, 32, 32);
> + break;
> + case GITS_CWRITER:
> + *data = extract64(s->cwriter, 0, 32);
> + break;
> + case GITS_CWRITER + 4:
> + *data = extract64(s->cwriter, 32, 32);
> + break;
> + case GITS_BASER ... GITS_BASER + 0x3f:
> + index = (offset - GITS_BASER) / 8;
> + if (offset & 7) {
> + *data = extract64(s->baser[index], 32, 32);
> + } else {
> + *data = extract64(s->baser[index], 0, 32);
> + }
> + break;
> + default:
> + result = MEMTX_ERROR;
> + break;
> + }
> return result;
> }
>
> @@ -57,7 +351,54 @@ static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
> uint64_t value, MemTxAttrs attrs)
> {
> MemTxResult result = MEMTX_OK;
> + int index;
>
> + switch (offset) {
> + case GITS_BASER ... GITS_BASER + 0x3f:
> + /*
> + * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is
> + * already enabled
> + */
> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> + index = (offset - GITS_BASER) / 8;
> + s->baser[index] &= GITS_BASER_RO_MASK;
> + s->baser[index] |= (value & ~GITS_BASER_RO_MASK);
> + }
> + break;
> + case GITS_CBASER:
> + /*
> + * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
> + * already enabled
> + */
> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> + s->cbaser = value;
> + s->creadr = 0;
> + s->cwriter = s->creadr;
> + }
> + break;
> + case GITS_CWRITER:
> + s->cwriter = value & ~R_GITS_CWRITER_RETRY_MASK;
> + break;
> + case GITS_CREADR:
> + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
> + s->creadr = value & ~R_GITS_CREADR_STALLED_MASK;
> + } else {
> + /* RO register, ignore the write */
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid guest write to RO register at offset "
> + TARGET_FMT_plx "\n", __func__, offset);
> + }
> + break;
> + case GITS_TYPER:
> + /* RO registers, ignore the write */
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid guest write to RO register at offset "
> + TARGET_FMT_plx "\n", __func__, offset);
> + break;
> + default:
> + result = MEMTX_ERROR;
> + break;
> + }
> return result;
> }
>
> @@ -65,7 +406,29 @@ static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
> uint64_t *data, MemTxAttrs attrs)
> {
> MemTxResult result = MEMTX_OK;
> + int index;
>
> + switch (offset) {
> + case GITS_TYPER:
> + *data = s->typer;
> + break;
> + case GITS_BASER ... GITS_BASER + 0x3f:
> + index = (offset - GITS_BASER) / 8;
> + *data = s->baser[index];
> + break;
> + case GITS_CBASER:
> + *data = s->cbaser;
> + break;
> + case GITS_CREADR:
> + *data = s->creadr;
> + break;
> + case GITS_CWRITER:
> + *data = s->cwriter;
> + break;
> + default:
> + result = MEMTX_ERROR;
> + break;
> + }
> return result;
> }
>
> @@ -162,6 +525,9 @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
> gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops);
>
> if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> + address_space_init(&s->gicv3->dma_as, s->gicv3->dma,
> + "gicv3-its-sysmem");
> +
> /* set the ITS default features supported */
> s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
> GITS_TYPE_PHYSICAL);
> @@ -208,6 +574,14 @@ static void gicv3_its_reset(DeviceState *dev)
> }
> }
>
> +static void gicv3_its_post_load(GICv3ITSState *s)
> +{
> + if (s->ctlr & ITS_CTLR_ENABLED) {
> + extract_table_params(s);
> + extract_cmdq_params(s);
> + }
> +}
> +
> static Property gicv3_its_props[] = {
> DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3",
> GICv3State *),
> @@ -218,10 +592,12 @@ static void gicv3_its_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
> + GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
>
> dc->realize = gicv3_arm_its_realize;
> device_class_set_props(dc, gicv3_its_props);
> device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
> + icc->post_load = gicv3_its_post_load;
> }
>
> static const TypeInfo gicv3_its_info = {
> diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
> index e0b06930a7..dc2c1bc45b 100644
> --- a/hw/intc/gicv3_internal.h
> +++ b/hw/intc/gicv3_internal.h
> @@ -238,7 +238,7 @@ FIELD(GITS_BASER, PAGESIZE, 8, 2)
> FIELD(GITS_BASER, SHAREABILITY, 10, 2)
> FIELD(GITS_BASER, PHYADDR, 12, 36)
> FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
> -FIELD(GITS_BASER, PHYADDRH_64K, 48, 4)
> +FIELD(GITS_BASER, PHYADDRH_64K, 12, 4)
should have been addressed earlier
> FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
> FIELD(GITS_BASER, OUTERCACHE, 53, 3)
> FIELD(GITS_BASER, TYPE, 56, 3)
> @@ -246,6 +246,20 @@ FIELD(GITS_BASER, INNERCACHE, 59, 3)
> FIELD(GITS_BASER, INDIRECT, 62, 1)
> FIELD(GITS_BASER, VALID, 63, 1)
>
> +FIELD(GITS_CBASER, SIZE, 0, 8)
> +FIELD(GITS_CBASER, SHAREABILITY, 10, 2)
> +FIELD(GITS_CBASER, PHYADDR, 12, 40)
> +FIELD(GITS_CBASER, OUTERCACHE, 53, 3)
> +FIELD(GITS_CBASER, INNERCACHE, 59, 3)
> +FIELD(GITS_CBASER, VALID, 63, 1)
> +
> +FIELD(GITS_CREADR, STALLED, 0, 1)
> +FIELD(GITS_CREADR, OFFSET, 5, 15)
> +
> +FIELD(GITS_CWRITER, RETRY, 0, 1)
> +FIELD(GITS_CWRITER, OFFSET, 5, 15)
> +
> +FIELD(GITS_CTLR, ENABLED, 0, 1)
> FIELD(GITS_CTLR, QUIESCENT, 31, 1)
>
> FIELD(GITS_TYPER, PHYSICAL, 0, 1)
> @@ -257,6 +271,13 @@ FIELD(GITS_TYPER, PTA, 19, 1)
> FIELD(GITS_TYPER, CIDBITS, 32, 4)
> FIELD(GITS_TYPER, CIL, 36, 1)
>
> +#define GITS_IDREGS 0xFFD0
> +
> +#define ITS_CTLR_ENABLED (1U) /* ITS Enabled */
> +
> +#define GITS_BASER_RO_MASK (R_GITS_BASER_ENTRYSIZE_MASK | \
> + R_GITS_BASER_TYPE_MASK)
> +
> #define GITS_BASER_PAGESIZE_4K 0
> #define GITS_BASER_PAGESIZE_16K 1
> #define GITS_BASER_PAGESIZE_64K 2
> @@ -264,6 +285,14 @@ FIELD(GITS_TYPER, CIL, 36, 1)
> #define GITS_ITT_TYPE_DEVICE 1ULL
> #define GITS_ITT_TYPE_COLLECTION 4ULL
>
> +#define GITS_PAGE_SIZE_4K 0x1000
> +#define GITS_PAGE_SIZE_16K 0x4000
> +#define GITS_PAGE_SIZE_64K 0x10000
> +
> +#define L1TABLE_ENTRY_SIZE 8
> +
> +#define GITS_CMDQ_ENTRY_SIZE 32
> +
> /**
> * Default features advertised by this version of ITS
> */
> diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
> index 91491a2f66..1fd5cedbbd 100644
> --- a/include/hw/intc/arm_gicv3_common.h
> +++ b/include/hw/intc/arm_gicv3_common.h
> @@ -226,6 +226,9 @@ struct GICv3State {
> int dev_fd; /* kvm device fd if backed by kvm vgic support */
> Error *migration_blocker;
>
> + MemoryRegion *dma;
> + AddressSpace dma_as;
> +
> /* Distributor */
>
> /* for a GIC with the security extensions the NS banked version of this
> diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
> index 65d1191db1..4e79145dde 100644
> --- a/include/hw/intc/arm_gicv3_its_common.h
> +++ b/include/hw/intc/arm_gicv3_its_common.h
> @@ -41,6 +41,25 @@
>
> #define GITS_TRANSLATER 0x0040
>
> +typedef struct {
> + bool valid;
> + bool indirect;
> + uint16_t entry_sz;
> + uint32_t page_sz;
> + uint32_t max_entries;
> + union {
> + uint32_t max_devids;
> + uint32_t max_collids;
> + } maxids;
> + uint64_t base_addr;
> +} TableDesc;
> +
> +typedef struct {
> + bool valid;
> + uint32_t max_entries;
> + uint64_t base_addr;
> +} CmdQDesc;
> +
> struct GICv3ITSState {
> SysBusDevice parent_obj;
>
> @@ -63,6 +82,10 @@ struct GICv3ITSState {
> uint64_t creadr;
> uint64_t baser[8];
>
> + TableDesc dt;
> + TableDesc ct;
> + CmdQDesc cq;
> +
> Error *migration_blocker;
> };
>
>
Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 03/10] hw/intc: GICv3 ITS command queue framework
2021-06-30 15:31 ` [PATCH v5 03/10] hw/intc: GICv3 ITS command queue framework Shashi Mallela
@ 2021-07-06 9:31 ` Eric Auger
0 siblings, 0 replies; 41+ messages in thread
From: Eric Auger @ 2021-07-06 9:31 UTC (permalink / raw)
To: Shashi Mallela, peter.maydell, leif, rad, mst, imammedo
Cc: qemu-arm, qemu-devel
Hi Shashi,
On 6/30/21 5:31 PM, Shashi Mallela wrote:
> Added functionality to trigger ITS command queue processing on
> write to CWRITE register and process each command queue entry to
> identify the command type and handle commands like MAPD,MAPC,SYNC.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/intc/arm_gicv3_its.c | 305 +++++++++++++++++++++++++++++++++++++++
> hw/intc/gicv3_internal.h | 37 +++++
> 2 files changed, 342 insertions(+)
>
> diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> index 2d786a1e21..5919d8d7b1 100644
> --- a/hw/intc/arm_gicv3_its.c
> +++ b/hw/intc/arm_gicv3_its.c
> @@ -49,6 +49,304 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
> return result;
> }
>
> +static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
> + uint64_t rdbase)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint64_t value;
> + uint64_t l2t_addr;
> + bool valid_l2t;
> + uint32_t l2t_id;
> + uint32_t max_l2_entries;
> + uint64_t cte = 0;
> + MemTxResult res = MEMTX_OK;
> +
> + if (!s->ct.valid) {
> + return res;
> + }
> +
> + if (valid) {
> + /* add mapping entry to collection table */
> + cte = (valid & TABLE_ENTRY_VALID_MASK) | (rdbase << 1ULL);
> + }
> +
> + /*
> + * The specification defines the format of level 1 entries of a
> + * 2-level table, but the format of level 2 entries and the format
> + * of flat-mapped tables is IMPDEF.
> + */
> + if (s->ct.indirect) {
> + l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
> +
> + value = address_space_ldq_le(as,
> + s->ct.base_addr +
> + (l2t_id * L1TABLE_ENTRY_SIZE),
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
> +
> + if (valid_l2t) {
> + max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
> +
> + l2t_addr = value & ((1ULL << 51) - 1);
> +
> + address_space_stq_le(as, l2t_addr +
> + ((icid % max_l2_entries) * GITS_CTE_SIZE),
> + cte, MEMTXATTRS_UNSPECIFIED, &res);
> + }
> + } else {
> + /* Flat level table */
> + address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE),
> + cte, MEMTXATTRS_UNSPECIFIED, &res);
> + }
> + return res;
> +}
> +
> +static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint16_t icid;
> + uint64_t rdbase;
> + bool valid;
> + MemTxResult res = MEMTX_OK;
> + uint64_t value;
> +
> + offset += NUM_BYTES_IN_DW;
> + offset += NUM_BYTES_IN_DW;
> +
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + icid = value & ICID_MASK;
> +
> + rdbase = (value >> R_MAPC_RDBASE_SHIFT) & RDBASE_PROCNUM_MASK;
unusual masking pattern
> +
> + valid = (value & CMD_FIELD_VALID_MASK);
> +
> + if ((icid > s->ct.maxids.max_collids) || (rdbase > s->gicv3->num_cpu)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "ITS MAPC: invalid collection table attributes "
> + "icid %d rdbase %lu\n", icid, rdbase);
> + /*
> + * in this implementation, in case of error
> + * we ignore this command and move onto the next
> + * command in the queue
> + */
> + } else {
> + res = update_cte(s, icid, valid, rdbase);
> + }
> +
> + return res;
> +}
> +
> +static MemTxResult update_dte(GICv3ITSState *s, uint32_t devid, bool valid,
> + uint8_t size, uint64_t itt_addr)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint64_t value;
> + uint64_t l2t_addr;
> + bool valid_l2t;
> + uint32_t l2t_id;
> + uint32_t max_l2_entries;
> + uint64_t dte = 0;
> + MemTxResult res = MEMTX_OK;
> +
> + if (s->dt.valid) {
> + if (valid) {
> + /* add mapping entry to device table */
> + dte = (valid & TABLE_ENTRY_VALID_MASK) |
> + ((size & SIZE_MASK) << 1U) |
> + ((itt_addr & ITTADDR_MASK) << 6ULL);
> + }
> + } else {
> + return res;
> + }
> +
> + /*
> + * The specification defines the format of level 1 entries of a
> + * 2-level table, but the format of level 2 entries and the format
> + * of flat-mapped tables is IMPDEF.
> + */
> + if (s->dt.indirect) {
> + l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
> +
> + value = address_space_ldq_le(as,
> + s->dt.base_addr +
> + (l2t_id * L1TABLE_ENTRY_SIZE),
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
> +
> + if (valid_l2t) {
> + max_l2_entries = s->dt.page_sz / s->dt.entry_sz;
> +
> + l2t_addr = value & ((1ULL << 51) - 1);
> +
> + address_space_stq_le(as, l2t_addr +
> + ((devid % max_l2_entries) * GITS_DTE_SIZE),
> + dte, MEMTXATTRS_UNSPECIFIED, &res);
> + }
> + } else {
> + /* Flat level table */
> + address_space_stq_le(as, s->dt.base_addr + (devid * GITS_DTE_SIZE),
> + dte, MEMTXATTRS_UNSPECIFIED, &res);
> + }
> + return res;
> +}
> +
> +static MemTxResult process_mapd(GICv3ITSState *s, uint64_t value,
> + uint32_t offset)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint32_t devid;
> + uint8_t size;
> + uint64_t itt_addr;
> + bool valid;
> + MemTxResult res = MEMTX_OK;
> +
> + devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> +
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + size = (value & SIZE_MASK);
> +
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + itt_addr = (value & ITTADDR_MASK) >> ITTADDR_SHIFT;
> +
> + valid = (value & CMD_FIELD_VALID_MASK);
> +
> + if ((devid > s->dt.maxids.max_devids) ||
> + (size > FIELD_EX64(s->typer, GITS_TYPER, IDBITS))) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "ITS MAPD: invalid device table attributes "
> + "devid %d or size %d\n", devid, size);
> + /*
> + * in this implementation, in case of error
> + * we ignore this command and move onto the next
> + * command in the queue
> + */
> + } else {
> + res = update_dte(s, devid, valid, size, itt_addr);
> + }
> +
> + return res;
> +}
> +
> +/*
> + * Current implementation blocks until all
> + * commands are processed
> + */
> +static void process_cmdq(GICv3ITSState *s)
> +{
> + uint32_t wr_offset = 0;
> + uint32_t rd_offset = 0;
> + uint32_t cq_offset = 0;
> + uint64_t data;
> + AddressSpace *as = &s->gicv3->dma_as;
> + MemTxResult res = MEMTX_OK;
> + uint8_t cmd;
> +
> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> + return;
> + }
> +
> + wr_offset = FIELD_EX64(s->cwriter, GITS_CWRITER, OFFSET);
> +
> + if (wr_offset > s->cq.max_entries) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid write offset "
> + "%d\n", __func__, wr_offset);
> + return;
> + }
> +
> + rd_offset = FIELD_EX64(s->creadr, GITS_CREADR, OFFSET);
> +
> + if (rd_offset > s->cq.max_entries) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid read offset "
> + "%d\n", __func__, rd_offset);
> + return;
> + }
> +
> + while (wr_offset != rd_offset) {
> + cq_offset = (rd_offset * GITS_CMDQ_ENTRY_SIZE);
> + data = address_space_ldq_le(as, s->cq.base_addr + cq_offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> + cmd = (data & CMD_MASK);
> +
> + switch (cmd) {
> + case GITS_CMD_INT:
> + break;
> + case GITS_CMD_CLEAR:
> + break;
> + case GITS_CMD_SYNC:
> + /*
> + * Current implementation makes a blocking synchronous call
> + * for every command issued earlier, hence the internal state
> + * is already consistent by the time SYNC command is executed.
> + * Hence no further processing is required for SYNC command.
> + */
> + break;
> + case GITS_CMD_MAPD:
> + res = process_mapd(s, data, cq_offset);
> + break;
> + case GITS_CMD_MAPC:
> + res = process_mapc(s, cq_offset);
> + break;
> + case GITS_CMD_MAPTI:
> + break;
> + case GITS_CMD_MAPI:
> + break;
> + case GITS_CMD_DISCARD:
> + break;
> + case GITS_CMD_INV:
> + case GITS_CMD_INVALL:
> + break;
> + default:
> + break;
> + }
> + if (res == MEMTX_OK) {
> + rd_offset++;
> + rd_offset %= s->cq.max_entries;
> + s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, OFFSET, rd_offset);
> + } else {
> + /*
> + * in this implementation, in case of dma read/write error
> + * we stall the command processing
> + */
> + s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, STALLED, 1);
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: %x cmd processing failed\n", __func__, cmd);
> + break;
> + }
> + }
> +}
> +
> /*
> * This function extracts the ITS Device and Collection table specific
> * parameters (like base_addr, size etc) from GITS_BASER register.
> @@ -205,6 +503,7 @@ static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
> extract_table_params(s);
> extract_cmdq_params(s);
> s->creadr = 0;
> + process_cmdq(s);
> }
> break;
> case GITS_CBASER:
> @@ -232,6 +531,9 @@ static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
> case GITS_CWRITER:
> s->cwriter = deposit64(s->cwriter, 0, 32,
> (value & ~R_GITS_CWRITER_RETRY_MASK));
> + if (s->cwriter != s->creadr) {
> + process_cmdq(s);
> + }
> break;
> case GITS_CWRITER + 4:
> s->cwriter = deposit64(s->cwriter, 32, 32, value);
> @@ -378,6 +680,9 @@ static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
> break;
> case GITS_CWRITER:
> s->cwriter = value & ~R_GITS_CWRITER_RETRY_MASK;
> + if (s->cwriter != s->creadr) {
> + process_cmdq(s);
> + }
> break;
> case GITS_CREADR:
> if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
> diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
> index dc2c1bc45b..a27b1e4d19 100644
> --- a/hw/intc/gicv3_internal.h
> +++ b/hw/intc/gicv3_internal.h
> @@ -292,6 +292,43 @@ FIELD(GITS_TYPER, CIL, 36, 1)
> #define L1TABLE_ENTRY_SIZE 8
>
> #define GITS_CMDQ_ENTRY_SIZE 32
> +#define NUM_BYTES_IN_DW 8
> +
> +#define CMD_MASK 0xff
> +
> +/* ITS Commands */
> +#define GITS_CMD_CLEAR 0x04
> +#define GITS_CMD_DISCARD 0x0F
> +#define GITS_CMD_INT 0x03
> +#define GITS_CMD_MAPC 0x09
> +#define GITS_CMD_MAPD 0x08
> +#define GITS_CMD_MAPI 0x0B
> +#define GITS_CMD_MAPTI 0x0A
> +#define GITS_CMD_INV 0x0C
> +#define GITS_CMD_INVALL 0x0D
> +#define GITS_CMD_SYNC 0x05
> +
> +/* MAPC command fields */
> +#define ICID_LENGTH 16
> +#define ICID_MASK ((1U << ICID_LENGTH) - 1)
> +FIELD(MAPC, RDBASE, 16, 32)
> +
> +#define RDBASE_PROCNUM_LENGTH 16
> +#define RDBASE_PROCNUM_MASK ((1ULL << RDBASE_PROCNUM_LENGTH) - 1)
> +
> +/* MAPD command fields */
> +#define ITTADDR_LENGTH 44
> +#define ITTADDR_SHIFT 8
> +#define ITTADDR_MASK ((1ULL << ITTADDR_LENGTH) - 1)
> +#define SIZE_MASK 0x1f
> +
> +#define DEVID_SHIFT 32
> +#define DEVID_MASK MAKE_64BIT_MASK(32, 32)
> +
> +#define VALID_SHIFT 63
> +#define CMD_FIELD_VALID_MASK (1ULL << VALID_SHIFT)
> +#define L2_TABLE_VALID_MASK CMD_FIELD_VALID_MASK
> +#define TABLE_ENTRY_VALID_MASK (1ULL << 0)
>
> /**
> * Default features advertised by this version of ITS
>
Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-06 3:25 ` shashi.mallela
2021-07-06 9:19 ` Peter Maydell
@ 2021-07-06 10:04 ` Eric Auger
2021-07-06 10:07 ` Peter Maydell
1 sibling, 1 reply; 41+ messages in thread
From: Eric Auger @ 2021-07-06 10:04 UTC (permalink / raw)
To: shashi.mallela, Peter Maydell
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
Hi Shashi, Peter,
On 7/6/21 5:25 AM, shashi.mallela@linaro.org wrote:
> On Mon, 2021-07-05 at 20:47 -0400, shashi.mallela@linaro.org wrote:
>> On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
>>> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
>>> shashi.mallela@linaro.org> wrote:
>>>> Added ITS command queue handling for MAPTI,MAPI commands,handled
>>>> ITS
>>>> translation which triggers an LPI via INT command as well as
>>>> write
>>>> to GITS_TRANSLATER register,defined enum to differentiate between
>>>> ITS
>>>> command interrupt trigger and GITS_TRANSLATER based interrupt
>>>> trigger.
>>>> Each of these commands make use of other functionalities
>>>> implemented to
>>>> get device table entry,collection table entry or interrupt
>>>> translation
>>>> table entry required for their processing.
>>>>
>>>> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
>>>> ---
>>>> +static MemTxResult process_mapti(GICv3ITSState *s, uint64_t
>>>> value,
>>>> + uint32_t offset, bool
>>>> ignore_pInt)
>>>> +{
>>>> + AddressSpace *as = &s->gicv3->dma_as;
>>>> + uint32_t devid, eventid;
>>>> + uint32_t pIntid = 0;
>>>> + uint32_t max_eventid, max_Intid;
>>>> + bool dte_valid;
>>>> + MemTxResult res = MEMTX_OK;
>>>> + uint16_t icid = 0;
>>>> + uint64_t dte = 0;
>>>> + IteEntry ite;
>>>> + uint32_t int_spurious = INTID_SPURIOUS;
>>>> + uint64_t idbits;
>>>> +
>>>> + devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
>>>> + offset += NUM_BYTES_IN_DW;
>>>> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
>>>> + MEMTXATTRS_UNSPECIFIED, &res);
>>>> +
>>>> + if (res != MEMTX_OK) {
>>>> + return res;
>>>> + }
>>>> +
>>>> + eventid = (value & EVENTID_MASK);
>>>> +
>>>> + if (!ignore_pInt) {
>>>> + pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT);
>>>> + }
>>>> +
>>>> + offset += NUM_BYTES_IN_DW;
>>>> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
>>>> + MEMTXATTRS_UNSPECIFIED, &res);
>>>> +
>>>> + if (res != MEMTX_OK) {
>>>> + return res;
>>>> + }
>>>> +
>>>> + icid = value & ICID_MASK;
>>>> +
>>>> + dte = get_dte(s, devid, &res);
>>>> +
>>>> + if (res != MEMTX_OK) {
>>>> + return res;
>>>> + }
>>>> + dte_valid = dte & TABLE_ENTRY_VALID_MASK;
>>>> +
>>>> + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
>>>> +
>>>> + if (!ignore_pInt) {
>>>> + idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser,
>>>> GICR_PROPBASER,
>>>> + IDBITS), GICD_TYPER_IDBITS);
>>>
>>> I missed this the first time around, but I don't think this is
>>> right.
>>> Different CPUs could have different GICR_PROPBASER values, so
>>> checking
>>> against just one of them is wrong.
"5.1.1 LPI configuration tables" says
"
It is IMPLEMENTATION DEFINED whether GICR_PROPBASER can be set to
different values on different
Redistributors. GICR_TYPER.CommonLPIAff indicates which Redistributors
must have GICR_PROPBASER set
to the same value whenever GICR_CTLR.EnableLPIs == 1.
"
So we can choose to set CommonLPIAff to 0 if we do not need to emulate
everything. This is what KVM does
Thanks
Eric
The pseudocode only tests
>>> LPIOutOfRange()
>>> which is documented as testing "larger than GICD_TYPER.IDbits or
>>> not
>>> in
>>> the LPI range and not 1023". So I don't think we should be looking
>>> at the GICR_PROPBASER field here.
>>>
>>> More generally, "s->gicv3->cpu->something" is usually going to be
>>> wrong, because it is implicitly looking at CPU 0; often either
>>> there
>>> should be something else telling is which CPU to use (as in
>>> &s->gicv3->cpu[rdbase] where the CTE told us which redistributor),
>>> or we might need to operate on all CPUs/redistributors. The only
>>> exception is where we can guarantee that all the CPUs are the same
>>> (eg when looking at GICR_TYPER.PLPIS.)
>> In that case,the validation of IDBITS(in case of ITS enabled) could
>> be
>> done during the write of gicr_propbaser register value itself(in
>> arm_gicv3_redist.c) and the its command processing code here can just
>> extract the idbits for its use.
>>> thanks
>>> -- PMM
> Hi Peter
>
> Please ignore my last comment.
>
> To address this scenario,i think the feasible option would be to call
> get_cte() to get the rdbase corresponding to icid value passed to mapti
> command.Since each icid is mapped to a rdbase(by virtue of calling MAPC
> command),if the collection table has a valid mapping for this icid we
> continue processing this MAPTI command using &s->gicv3->cpu[rdbase]
> applicable propbaser value to validate idbits, else return without
> further processing.
>
> Thanks
> Shashi
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-06-30 15:31 ` [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing Shashi Mallela
2021-07-05 14:07 ` Peter Maydell
2021-07-05 14:54 ` Peter Maydell
@ 2021-07-06 10:05 ` Eric Auger
2 siblings, 0 replies; 41+ messages in thread
From: Eric Auger @ 2021-07-06 10:05 UTC (permalink / raw)
To: Shashi Mallela, peter.maydell, leif, rad, mst, imammedo
Cc: qemu-arm, qemu-devel
Hi Shashi,
On 6/30/21 5:31 PM, Shashi Mallela wrote:
> Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
> translation which triggers an LPI via INT command as well as write
> to GITS_TRANSLATER register,defined enum to differentiate between ITS
> command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
> Each of these commands make use of other functionalities implemented to
> get device table entry,collection table entry or interrupt translation
> table entry required for their processing.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> ---
> hw/intc/arm_gicv3_its.c | 361 ++++++++++++++++++++++++++++-
> hw/intc/gicv3_internal.h | 26 +++
> include/hw/intc/arm_gicv3_common.h | 2 +
> 3 files changed, 388 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> index 5919d8d7b1..adaee72c1f 100644
> --- a/hw/intc/arm_gicv3_its.c
> +++ b/hw/intc/arm_gicv3_its.c
> @@ -28,6 +28,22 @@ struct GICv3ITSClass {
> void (*parent_reset)(DeviceState *dev);
> };
>
> +/*
> + * This is an internal enum used to distinguish between LPI triggered
> + * via command queue and LPI triggered via gits_translater write.
> + */
> +typedef enum ItsCmdType {
> + NONE = 0, /* internal indication for GITS_TRANSLATER write */
> + CLEAR = 1,
> + DISCARD = 2,
> + INT = 3,
> +} ItsCmdType;
> +
> +typedef struct {
> + uint32_t iteh;
> + uint64_t itel;
> +} IteEntry;
> +
> static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
> {
> uint64_t result = 0;
> @@ -49,6 +65,330 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
> return result;
> }
>
> +static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte,
> + MemTxResult *res)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint64_t l2t_addr;
> + uint64_t value;
> + bool valid_l2t;
> + uint32_t l2t_id;
> + uint32_t max_l2_entries;
> +
> + if (s->ct.indirect) {
> + l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
> +
> + value = address_space_ldq_le(as,
> + s->ct.base_addr +
> + (l2t_id * L1TABLE_ENTRY_SIZE),
> + MEMTXATTRS_UNSPECIFIED, res);
> +
> + if (*res == MEMTX_OK) {
> + valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
> +
> + if (valid_l2t) {
> + max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
> +
> + l2t_addr = value & ((1ULL << 51) - 1);
> +
> + *cte = address_space_ldq_le(as, l2t_addr +
> + ((icid % max_l2_entries) * GITS_CTE_SIZE),
> + MEMTXATTRS_UNSPECIFIED, res);
> + }
> + }
> + } else {
> + /* Flat level table */
> + *cte = address_space_ldq_le(as, s->ct.base_addr +
> + (icid * GITS_CTE_SIZE),
> + MEMTXATTRS_UNSPECIFIED, res);
> + }
> +
> + return (*cte & TABLE_ENTRY_VALID_MASK) != 0;
> +}
> +
> +static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
> + IteEntry ite)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint64_t itt_addr;
> + MemTxResult res = MEMTX_OK;
> +
> + itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
usual mask scheme
> + itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
> +
> + address_space_stq_le(as, itt_addr + (eventid * sizeof(uint64_t)),
> + ite.itel, MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res == MEMTX_OK) {
> + address_space_stl_le(as, itt_addr + ((eventid + sizeof(uint64_t)) *
> + sizeof(uint32_t)), ite.iteh,
> + MEMTXATTRS_UNSPECIFIED, &res);
> + }
> + return res;
> +}
> +
> +static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
> + uint16_t *icid, uint32_t *pIntid, MemTxResult *res)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint64_t itt_addr;
> + bool status = false;
> + IteEntry ite;
> +
> + itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
usual mask scheme
> + itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
> +
> + memset(&ite, 0 , sizeof(ite));
nit you could have initialized ite directly = {}.
> + ite.itel = address_space_ldq_le(as, itt_addr +
> + (eventid * sizeof(uint64_t)),
> + MEMTXATTRS_UNSPECIFIED, res);
> +
> + if (*res == MEMTX_OK) {
> + ite.iteh = address_space_ldl_le(as, itt_addr + ((eventid +
> + sizeof(uint64_t)) * sizeof(uint32_t)),
> + MEMTXATTRS_UNSPECIFIED, res);
> +
> + if (*res == MEMTX_OK) {
> + if (ite.itel & TABLE_ENTRY_VALID_MASK) {
> + if ((ite.itel >> ITE_ENTRY_INTTYPE_SHIFT) &
> + GITS_TYPE_PHYSICAL) {
> + *pIntid = (ite.itel >> ITE_ENTRY_INTID_SHIFT) &
> + ITE_ENTRY_INTID_MASK;
> + *icid = ite.iteh & ITE_ENTRY_ICID_MASK;
> + status = true;
> + }
> + }
> + }
> + }
> + return status;
> +}
> +
> +static uint64_t get_dte(GICv3ITSState *s, uint32_t devid, MemTxResult *res)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint64_t l2t_addr;
> + uint64_t value;
> + bool valid_l2t;
> + uint32_t l2t_id;
> + uint32_t max_l2_entries;
> +
> + if (s->dt.indirect) {
> + l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
> +
> + value = address_space_ldq_le(as,
> + s->dt.base_addr +
> + (l2t_id * L1TABLE_ENTRY_SIZE),
> + MEMTXATTRS_UNSPECIFIED, res);
> +
> + if (*res == MEMTX_OK) {
> + valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
> +
> + if (valid_l2t) {
> + max_l2_entries = s->dt.page_sz / s->dt.entry_sz;
> +
> + l2t_addr = value & ((1ULL << 51) - 1);
> +
> + value = address_space_ldq_le(as, l2t_addr +
> + ((devid % max_l2_entries) * GITS_DTE_SIZE),
> + MEMTXATTRS_UNSPECIFIED, res);
> + }
> + }
> + } else {
> + /* Flat level table */
> + value = address_space_ldq_le(as, s->dt.base_addr +
> + (devid * GITS_DTE_SIZE),
> + MEMTXATTRS_UNSPECIFIED, res);
> + }
> +
> + return value;
> +}
> +
> +/*
> + * This function handles the processing of following commands based on
> + * the ItsCmdType parameter passed:-
> + * 1. trigerring of lpi interrupt translation via ITS INT command
> + * 2. trigerring of lpi interrupt translation via gits_translater register
> + * 3. handling of ITS CLEAR command
> + * 4. handling of ITS DISCARD command
> + */
> +static MemTxResult process_its_cmd(GICv3ITSState *s, uint64_t value,
> + uint32_t offset, ItsCmdType cmd)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint32_t devid, eventid;
> + MemTxResult res = MEMTX_OK;
> + bool dte_valid;
> + uint64_t dte = 0;
> + uint32_t max_eventid;
> + uint16_t icid = 0;
> + uint32_t pIntid = 0;
> + bool ite_valid = false;
> + uint64_t cte = 0;
> + bool cte_valid = false;
> + IteEntry ite;
> +
> + if (cmd == NONE) {
> + devid = offset;
> + } else {> + devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> +
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> + }
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + eventid = (value & EVENTID_MASK);
> +
> + dte = get_dte(s, devid, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> + dte_valid = dte & TABLE_ENTRY_VALID_MASK;
> +
> + if (dte_valid) {
> + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> +
> + ite_valid = get_ite(s, eventid, dte, &icid, &pIntid, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + if (ite_valid) {
> + cte_valid = get_cte(s, icid, &cte, &res);
> + }
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> + }
> +
> + if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid ||
> + !cte_valid || (eventid > max_eventid)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid command attributes "
> + "devid %d or eventid %d or invalid dte %d or"
> + "invalid cte %d or invalid ite %d\n",
> + __func__, devid, eventid, dte_valid, cte_valid,
> + ite_valid);
> + /*
> + * in this implementation, in case of error
> + * we ignore this command and move onto the next
> + * command in the queue
> + */
> + } else {
> + /*
> + * Current implementation only supports rdbase == procnum
> + * Hence rdbase physical address is ignored
> + */
> + if (cmd == DISCARD) {
> + memset(&ite, 0 , sizeof(ite));
> + /* remove mapping from interrupt translation table */
> + res = update_ite(s, eventid, dte, ite);
> + }
> + }
> +
> + return res;
> +}
> +
> +static MemTxResult process_mapti(GICv3ITSState *s, uint64_t value,
> + uint32_t offset, bool ignore_pInt)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint32_t devid, eventid;
> + uint32_t pIntid = 0;
> + uint32_t max_eventid, max_Intid;
> + bool dte_valid;
> + MemTxResult res = MEMTX_OK;
> + uint16_t icid = 0;
> + uint64_t dte = 0;
> + IteEntry ite;
> + uint32_t int_spurious = INTID_SPURIOUS;
> + uint64_t idbits;
> +
> + devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + eventid = (value & EVENTID_MASK);
> +
> + if (!ignore_pInt) {
> + pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT);
> + }
> +
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + icid = value & ICID_MASK;
> +
> + dte = get_dte(s, devid, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> + dte_valid = dte & TABLE_ENTRY_VALID_MASK;
> +
> + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> +
> + if (!ignore_pInt) {
> + idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser, GICR_PROPBASER,
> + IDBITS), GICD_TYPER_IDBITS);
> +
> + if (idbits < GICR_PROPBASER_IDBITS_THRESHOLD) {
> + return res;
> + }
> + max_Intid = (1ULL << (idbits + 1));
> + }
> +
> + if ((devid > s->dt.maxids.max_devids) || (icid > s->ct.maxids.max_collids)
> + || !dte_valid || (eventid > max_eventid) ||
> + (!ignore_pInt && ((pIntid < GICV3_LPI_INTID_START) ||
> + (pIntid > max_Intid)))) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid command attributes "
> + "devid %d or icid %d or eventid %d or pIntid %d or"
> + "unmapped dte %d\n", __func__, devid, icid, eventid,
> + pIntid, dte_valid);
> + /*
> + * in this implementation, in case of error
> + * we ignore this command and move onto the next
> + * command in the queue
> + */
> + } else {
> + memset(&ite, 0 , sizeof(ite));
> + /* add ite entry to interrupt translation table */
> + ite.itel = (dte_valid & TABLE_ENTRY_VALID_MASK) |
> + (GITS_TYPE_PHYSICAL << ITE_ENTRY_INTTYPE_SHIFT);
> +
> + if (ignore_pInt) {
> + ite.itel |= (eventid << ITE_ENTRY_INTID_SHIFT);
> + } else {
> + ite.itel |= (pIntid << ITE_ENTRY_INTID_SHIFT);
> + }
> + ite.itel |= (int_spurious << ITE_ENTRY_INTSP_SHIFT);
> + ite.iteh |= icid;
> +
> + res = update_ite(s, eventid, dte, ite);
> + }
> +
> + return res;
> +}
> +
> static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
> uint64_t rdbase)
> {
> @@ -127,7 +467,8 @@ static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
>
> icid = value & ICID_MASK;
>
> - rdbase = (value >> R_MAPC_RDBASE_SHIFT) & RDBASE_PROCNUM_MASK;
> + rdbase = (value & R_MAPC_RDBASE_MASK) >> R_MAPC_RDBASE_SHIFT;
> + rdbase &= RDBASE_PROCNUM_MASK;
>
> valid = (value & CMD_FIELD_VALID_MASK);
>
> @@ -301,8 +642,10 @@ static void process_cmdq(GICv3ITSState *s)
>
> switch (cmd) {
> case GITS_CMD_INT:
> + res = process_its_cmd(s, data, cq_offset, INT);
> break;
> case GITS_CMD_CLEAR:
> + res = process_its_cmd(s, data, cq_offset, CLEAR);
> break;
> case GITS_CMD_SYNC:
> /*
> @@ -319,10 +662,13 @@ static void process_cmdq(GICv3ITSState *s)
> res = process_mapc(s, cq_offset);
> break;
> case GITS_CMD_MAPTI:
> + res = process_mapti(s, data, cq_offset, false);
> break;
> case GITS_CMD_MAPI:
> + res = process_mapti(s, data, cq_offset, true);
> break;
> case GITS_CMD_DISCARD:
> + res = process_its_cmd(s, data, cq_offset, DISCARD);
> break;
> case GITS_CMD_INV:
> case GITS_CMD_INVALL:
> @@ -484,7 +830,20 @@ static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
> uint64_t data, unsigned size,
> MemTxAttrs attrs)
> {
> + GICv3ITSState *s = (GICv3ITSState *)opaque;
> MemTxResult result = MEMTX_OK;
> + uint32_t devid = 0;
> +
> + switch (offset) {
> + case GITS_TRANSLATER:
> + if (s->ctlr & ITS_CTLR_ENABLED) {
> + devid = attrs.requester_id;
> + result = process_its_cmd(s, data, devid, NONE);
> + }
> + break;
> + default:
> + break;
> + }
>
> return result;
> }
> diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
> index a27b1e4d19..f7675a5adc 100644
> --- a/hw/intc/gicv3_internal.h
> +++ b/hw/intc/gicv3_internal.h
> @@ -123,6 +123,20 @@
> #define GICR_TYPER_COMMONLPIAFF (0x3 << 24)
> #define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32)
>
> +FIELD(GICR_PROPBASER, IDBITS, 0, 5)
> +FIELD(GICR_PROPBASER, INNERCACHE, 7, 3)
> +FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2)
> +FIELD(GICR_PROPBASER, PHYADDR, 12, 40)
> +FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3)
> +
> +#define GICR_PROPBASER_IDBITS_THRESHOLD 0xd
> +
> +FIELD(GICR_PENDBASER, INNERCACHE, 7, 3)
> +FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2)
> +FIELD(GICR_PENDBASER, PHYADDR, 16, 36)
> +FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3)
> +FIELD(GICR_PENDBASER, PTZ, 62, 1)
> +
> #define GICR_WAKER_ProcessorSleep (1U << 1)
> #define GICR_WAKER_ChildrenAsleep (1U << 2)
>
> @@ -322,6 +336,13 @@ FIELD(MAPC, RDBASE, 16, 32)
> #define ITTADDR_MASK ((1ULL << ITTADDR_LENGTH) - 1)
> #define SIZE_MASK 0x1f
>
> +/* MAPI command fields */
> +#define EVENTID_MASK ((1ULL << 32) - 1)
> +
> +/* MAPTI command fields */
> +#define pINTID_SHIFT 32
> +#define pINTID_MASK MAKE_64BIT_MASK(32, 32)
> +
> #define DEVID_SHIFT 32
> #define DEVID_MASK MAKE_64BIT_MASK(32, 32)
>
> @@ -347,6 +368,11 @@ FIELD(MAPC, RDBASE, 16, 32)
> * vPEID = 16 bits
> */
> #define ITS_ITT_ENTRY_SIZE 0xC
> +#define ITE_ENTRY_INTTYPE_SHIFT 1
> +#define ITE_ENTRY_INTID_SHIFT 2
> +#define ITE_ENTRY_INTID_MASK ((1ULL << 24) - 1)
> +#define ITE_ENTRY_INTSP_SHIFT 26
> +#define ITE_ENTRY_ICID_MASK ((1ULL << 16) - 1)
>
> /* 16 bits EventId */
> #define ITS_IDBITS GICD_TYPER_IDBITS
> diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
> index 1fd5cedbbd..0715b0bc2a 100644
> --- a/include/hw/intc/arm_gicv3_common.h
> +++ b/include/hw/intc/arm_gicv3_common.h
> @@ -36,6 +36,8 @@
> #define GICV3_MAXIRQ 1020
> #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
>
> +#define GICV3_LPI_INTID_START 8192
> +
> #define GICV3_REDIST_SIZE 0x20000
>
> /* Number of SGI target-list bits */
>
Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-06 10:04 ` Eric Auger
@ 2021-07-06 10:07 ` Peter Maydell
0 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2021-07-06 10:07 UTC (permalink / raw)
To: Eric Auger
Cc: Michael S. Tsirkin, Shashi Mallela, Radoslaw Biernacki,
QEMU Developers, qemu-arm, Igor Mammedov, Leif Lindholm
On Tue, 6 Jul 2021 at 11:04, Eric Auger <eauger@redhat.com> wrote:
>
> Hi Shashi, Peter,
>
> On 7/6/21 5:25 AM, shashi.mallela@linaro.org wrote:
> > On Mon, 2021-07-05 at 20:47 -0400, shashi.mallela@linaro.org wrote:
> >> On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> >>> I missed this the first time around, but I don't think this is
> >>> right.
> >>> Different CPUs could have different GICR_PROPBASER values, so
> >>> checking
> >>> against just one of them is wrong.
>
> "5.1.1 LPI configuration tables" says
>
> "
> It is IMPLEMENTATION DEFINED whether GICR_PROPBASER can be set to
> different values on different
> Redistributors. GICR_TYPER.CommonLPIAff indicates which Redistributors
> must have GICR_PROPBASER set
> to the same value whenever GICR_CTLR.EnableLPIs == 1.
> "
>
> So we can choose to set CommonLPIAff to 0 if we do not need to emulate
> everything. This is what KVM does
We could choose to do that, but as it happens we don't.
And as far as I can tell from the spec we should not be looking
at GICR_PROPBASER at all here anyway.
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-06 9:19 ` Peter Maydell
@ 2021-07-06 12:46 ` shashi.mallela
2021-07-06 13:27 ` Peter Maydell
0 siblings, 1 reply; 41+ messages in thread
From: shashi.mallela @ 2021-07-06 12:46 UTC (permalink / raw)
To: Peter Maydell
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Tue, 2021-07-06 at 10:19 +0100, Peter Maydell wrote:
> On Tue, 6 Jul 2021 at 04:25, <shashi.mallela@linaro.org> wrote:
> > On Mon, 2021-07-05 at 20:47 -0400, shashi.mallela@linaro.org wrote:
> > > On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> > > > I missed this the first time around, but I don't think this is
> > > > right.
> > > > Different CPUs could have different GICR_PROPBASER values, so
> > > > checking
> > > > against just one of them is wrong. The pseudocode only tests
> > > > LPIOutOfRange()
> > > > which is documented as testing "larger than GICD_TYPER.IDbits
> > > > or
> > > > not
> > > > in
> > > > the LPI range and not 1023". So I don't think we should be
> > > > looking
> > > > at the GICR_PROPBASER field here.
> > > >
> > > > More generally, "s->gicv3->cpu->something" is usually going to
> > > > be
> > > > wrong, because it is implicitly looking at CPU 0; often either
> > > > there
> > > > should be something else telling is which CPU to use (as in
> > > > &s->gicv3->cpu[rdbase] where the CTE told us which
> > > > redistributor),
> > > > or we might need to operate on all CPUs/redistributors. The
> > > > only
> > > > exception is where we can guarantee that all the CPUs are the
> > > > same
> > > > (eg when looking at GICR_TYPER.PLPIS.)
> > Please ignore my last comment.
> >
> > To address this scenario,i think the feasible option would be to
> > call
> > get_cte() to get the rdbase corresponding to icid value passed to
> > mapti
> > command.Since each icid is mapped to a rdbase(by virtue of calling
> > MAPC
> > command),if the collection table has a valid mapping for this icid
> > we
> > continue processing this MAPTI command using &s->gicv3->cpu[rdbase]
> > applicable propbaser value to validate idbits, else return without
> > further processing.
>
> But the pseudocode for MAPTI does not say anywhere that we should
> be checking the pIntID against any CPU's GICR_PROPBASER field.
> It is checked only by the checks in LPIOutOfRange(), which tests:
> * is it larger than permitted by GICD_TYPER.IDbits
> * is it not in the LPI range and not 1023
>
> Checking whether the intID is too big and would cause us to index
> off the end of the redistributor's configuration table should be done
> later, only when the ITS actually sends the interrupt to a particular
> redistributor, I think.
>
> (You can't rely on the guest having done the MAPC before the MAPTI;
> and in any case the guest could choose to do a MAPC to a different
> redistributor after it's done the MAPTI.)
>
> thanks
> -- PMM
We already have the "intID too big check" in place within the
redistributor processing when ITS sends the interrupt trigger.
"the LPI range and not 1023" is also handled in this function,but for
validating "is it larger than permitted by GICD_TYPER.IDbits",the
source of GICD_TYPER.IDbits is GICR_PROPBASER because we pick up min of
GICR_PROPBASER.IDbits and GICD_TYPER.IDBits.
If we are to not use gicr_propbaser,then are we good to just accept the
intID value here since we are validating the same during interrupt
processing?
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-06 12:46 ` shashi.mallela
@ 2021-07-06 13:27 ` Peter Maydell
2021-07-07 2:08 ` shashi.mallela
0 siblings, 1 reply; 41+ messages in thread
From: Peter Maydell @ 2021-07-06 13:27 UTC (permalink / raw)
To: Shashi Mallela
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Tue, 6 Jul 2021 at 13:46, <shashi.mallela@linaro.org> wrote:
>
> On Tue, 2021-07-06 at 10:19 +0100, Peter Maydell wrote:
> > On Tue, 6 Jul 2021 at 04:25, <shashi.mallela@linaro.org> wrote:
> >
> > But the pseudocode for MAPTI does not say anywhere that we should
> > be checking the pIntID against any CPU's GICR_PROPBASER field.
> > It is checked only by the checks in LPIOutOfRange(), which tests:
> > * is it larger than permitted by GICD_TYPER.IDbits
> > * is it not in the LPI range and not 1023
> >
> > Checking whether the intID is too big and would cause us to index
> > off the end of the redistributor's configuration table should be done
> > later, only when the ITS actually sends the interrupt to a particular
> > redistributor, I think.
> >
> > (You can't rely on the guest having done the MAPC before the MAPTI;
> > and in any case the guest could choose to do a MAPC to a different
> > redistributor after it's done the MAPTI.)
> We already have the "intID too big check" in place within the
> redistributor processing when ITS sends the interrupt trigger.
> "the LPI range and not 1023" is also handled in this function,but for
> validating "is it larger than permitted by GICD_TYPER.IDbits",the
> source of GICD_TYPER.IDbits is GICR_PROPBASER because we pick up min of
> GICR_PROPBASER.IDbits and GICD_TYPER.IDBits.
>
> If we are to not use gicr_propbaser,then are we good to just accept the
> intID value here since we are validating the same during interrupt
> processing?
You should check the things the pseudocode says you should check.
When processing MAPTI, that's GICD_TYPER.IDbits. GICR_PROPBASER.IDbits
is not the same thing because the guest can set it to a smaller value.
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-06 9:27 ` Eric Auger
@ 2021-07-07 2:02 ` shashi.mallela
0 siblings, 0 replies; 41+ messages in thread
From: shashi.mallela @ 2021-07-07 2:02 UTC (permalink / raw)
To: Eric Auger, Peter Maydell
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Tue, 2021-07-06 at 11:27 +0200, Eric Auger wrote:
> Hi,
>
> On 7/5/21 4:07 PM, Peter Maydell wrote:
> > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > shashi.mallela@linaro.org> wrote:
> > > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > > ITS
> > > translation which triggers an LPI via INT command as well as
> > > write
> > > to GITS_TRANSLATER register,defined enum to differentiate between
> > > ITS
> > > command interrupt trigger and GITS_TRANSLATER based interrupt
> > > trigger.
> > > Each of these commands make use of other functionalities
> > > implemented to
> > > get device table entry,collection table entry or interrupt
> > > translation
> > > table entry required for their processing.
> > >
> > > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > > ---
> > > hw/intc/arm_gicv3_its.c | 361
> > > ++++++++++++++++++++++++++++-
> > > hw/intc/gicv3_internal.h | 26 +++
> > > include/hw/intc/arm_gicv3_common.h | 2 +
> > > 3 files changed, 388 insertions(+), 1 deletion(-)
> > > +/*
> > > + * This function handles the processing of following commands
> > > based on
> > > + * the ItsCmdType parameter passed:-
> > > + * 1. trigerring of lpi interrupt translation via ITS INT
> > > command
> > > + * 2. trigerring of lpi interrupt translation via
> > > gits_translater register
> > > + * 3. handling of ITS CLEAR command
> > > + * 4. handling of ITS DISCARD command
> > > + */
> >
> > "triggering"
> >
> > > #define DEVID_SHIFT 32
> > > #define DEVID_MASK MAKE_64BIT_MASK(32, 32)
> > > @@ -347,6 +368,11 @@ FIELD(MAPC, RDBASE, 16, 32)
> > > * vPEID = 16 bits
> > > */
> > > #define ITS_ITT_ENTRY_SIZE 0xC
> > > +#define ITE_ENTRY_INTTYPE_SHIFT 1
> > > +#define ITE_ENTRY_INTID_SHIFT 2
> > > +#define ITE_ENTRY_INTID_MASK ((1ULL << 24) - 1)
> > > +#define ITE_ENTRY_INTSP_SHIFT 26
> > > +#define ITE_ENTRY_ICID_MASK ((1ULL << 16) - 1)
> >
> > This is still using a MASK value that's at the bottom of the
> > integer, not in its shifted location.
> There are other locations, pointed out by former comments, where this
> kind of unusual masking scheme is used but well...
Have taken care of masking scheme as desired in all relevant sections
in v6 patch
>
> Thanks
>
> Eric
>
> > Otherwise
> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> >
> > thanks
> > -- PMM
> >
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
2021-07-06 7:44 ` Eric Auger
@ 2021-07-07 2:06 ` shashi.mallela
0 siblings, 0 replies; 41+ messages in thread
From: shashi.mallela @ 2021-07-07 2:06 UTC (permalink / raw)
To: Eric Auger, peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
On Tue, 2021-07-06 at 09:44 +0200, Eric Auger wrote:
> Hi,
>
> On 6/30/21 5:31 PM, Shashi Mallela wrote:
> > Added register definitions relevant to ITS,implemented overall
> > ITS device framework with stubs for ITS control and translater
> > regions read/write,extended ITS common to handle mmio init between
> > existing kvm device and newer qemu device.
> >
> > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> Some of my comments in v4 were not commented nor addressed in v5.
>
> Also here and in the other respinned patches, please add an
> individual
> history log to track the major changes you made from n-1 to n to help
> the review.
Have addressed all the pending v4 comments and summarized all major
changes in v6 series in the cover-letter section
> Thanks
>
> Eric
> > ---
> > hw/intc/arm_gicv3_its.c | 240
> > +++++++++++++++++++++++++
> > hw/intc/arm_gicv3_its_common.c | 7 +-
> > hw/intc/arm_gicv3_its_kvm.c | 2 +-
> > hw/intc/gicv3_internal.h | 88 +++++++--
> > hw/intc/meson.build | 1 +
> > include/hw/intc/arm_gicv3_its_common.h | 9 +-
> > 6 files changed, 331 insertions(+), 16 deletions(-)
> > create mode 100644 hw/intc/arm_gicv3_its.c
> >
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > new file mode 100644
> > index 0000000000..545cda3665
> > --- /dev/null
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -0,0 +1,240 @@
> > +/*
> > + * ITS emulation for a GICv3-based system
> > + *
> > + * Copyright Linaro.org 2021
> > + *
> > + * Authors:
> > + * Shashi Mallela <shashi.mallela@linaro.org>
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2
> > or (at your
> > + * option) any later version. See the COPYING file in the top-
> > level directory.
> > + *
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/intc/arm_gicv3_its_common.h"
> > +#include "gicv3_internal.h"
> > +#include "qom/object.h"
> > +
> > +typedef struct GICv3ITSClass GICv3ITSClass;
> > +/* This is reusing the GICv3ITSState typedef from
> > ARM_GICV3_ITS_COMMON */
> > +DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
> > + ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
> > +
> > +struct GICv3ITSClass {
> > + GICv3ITSCommonClass parent_class;
> > + void (*parent_reset)(DeviceState *dev);
> > +};
> > +
> > +static MemTxResult gicv3_its_translation_write(void *opaque,
> > hwaddr offset,
> > + uint64_t data,
> > unsigned size,
> > + MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
> > + uint64_t value, MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
> > + uint64_t *data, MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
> > + uint64_t value, MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
> > + uint64_t *data, MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult gicv3_its_read(void *opaque, hwaddr offset,
> > uint64_t *data,
> > + unsigned size, MemTxAttrs attrs)
> > +{
> > + GICv3ITSState *s = (GICv3ITSState *)opaque;
> > + MemTxResult result;
> > +
> > + switch (size) {
> > + case 4:
> > + result = its_readl(s, offset, data, attrs);
> > + break;
> > + case 8:
> > + result = its_readll(s, offset, data, attrs);
> > + break;
> > + default:
> > + result = MEMTX_ERROR;
> > + break;
> > + }
> > +
> > + if (result == MEMTX_ERROR) {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: invalid guest read at offset "
> > TARGET_FMT_plx
> > + "size %u\n", __func__, offset, size);
> > + /*
> > + * The spec requires that reserved registers are RAZ/WI;
> > + * so use MEMTX_ERROR returns from leaf functions as a way
> > to
> > + * trigger the guest-error logging but don't return it to
> > + * the caller, or we'll cause a spurious guest data abort.
> > + */
> > + result = MEMTX_OK;
> > + *data = 0;
> > + }
> > + return result;
> > +}
> > +
> > +static MemTxResult gicv3_its_write(void *opaque, hwaddr offset,
> > uint64_t data,
> > + unsigned size, MemTxAttrs
> > attrs)
> > +{
> > + GICv3ITSState *s = (GICv3ITSState *)opaque;
> > + MemTxResult result;
> > +
> > + switch (size) {
> > + case 4:
> > + result = its_writel(s, offset, data, attrs);
> > + break;
> > + case 8:
> > + result = its_writell(s, offset, data, attrs);
> > + break;
> > + default:
> > + result = MEMTX_ERROR;
> > + break;
> > + }
> > +
> > + if (result == MEMTX_ERROR) {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: invalid guest write at offset "
> > TARGET_FMT_plx
> > + "size %u\n", __func__, offset, size);
> > + /*
> > + * The spec requires that reserved registers are RAZ/WI;
> > + * so use MEMTX_ERROR returns from leaf functions as a way
> > to
> > + * trigger the guest-error logging but don't return it to
> > + * the caller, or we'll cause a spurious guest data abort.
> > + */
> > + result = MEMTX_OK;
> > + }
> > + return result;
> > +}
> > +
> > +static const MemoryRegionOps gicv3_its_control_ops = {
> > + .read_with_attrs = gicv3_its_read,
> > + .write_with_attrs = gicv3_its_write,
> > + .valid.min_access_size = 4,
> > + .valid.max_access_size = 8,
> > + .impl.min_access_size = 4,
> > + .impl.max_access_size = 8,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > +};
> > +
> > +static const MemoryRegionOps gicv3_its_translation_ops = {
> > + .write_with_attrs = gicv3_its_translation_write,
> > + .valid.min_access_size = 2,
> > + .valid.max_access_size = 4,
> > + .impl.min_access_size = 2,
> > + .impl.max_access_size = 4,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > +};
> > +
> > +static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
> > +{
> > + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > +
> > + gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > &gicv3_its_translation_ops);
> > +
> > + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> > + /* set the ITS default features supported */
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
> > + GITS_TYPE_PHYSICAL);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER,
> > ITT_ENTRY_SIZE,
> > + ITS_ITT_ENTRY_SIZE - 1);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS,
> > ITS_IDBITS);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS,
> > ITS_DEVBITS);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1);
> > + s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS,
> > ITS_CIDBITS);
> > + }
> > +}
> > +
> > +static void gicv3_its_reset(DeviceState *dev)
> > +{
> > + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > + GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
> > +
> > + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> > + c->parent_reset(dev);
> > +
> > + /* Quiescent bit reset to 1 */
> > + s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
> > +
> > + /*
> > + * setting GITS_BASER0.Type = 0b001 (Device)
> > + * GITS_BASER1.Type = 0b100 (Collection Table)
> > + * GITS_BASER<n>.Type,where n = 3 to 7 are 0b00
> > (Unimplemented)
> > + * GITS_BASER<0,1>.Page_Size = 64KB
> > + * and default translation table entry size to 16 bytes
> > + */
> > + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE,
> > + GITS_ITT_TYPE_DEVICE);
> > + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER,
> > PAGESIZE,
> > + GITS_BASER_PAGESIZE_64K);
> > + s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER,
> > ENTRYSIZE,
> > + GITS_DTE_SIZE - 1);
> > +
> > + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE,
> > + GITS_ITT_TYPE_COLLECTION);
> > + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER,
> > PAGESIZE,
> > + GITS_BASER_PAGESIZE_64K);
> > + s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER,
> > ENTRYSIZE,
> > + GITS_CTE_SIZE - 1);
> > + }
> > +}
> > +
> > +static Property gicv3_its_props[] = {
> > + DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-
> > gicv3",
> > + GICv3State *),
> > + DEFINE_PROP_END_OF_LIST(),
> > +};
> > +
> > +static void gicv3_its_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
> > +
> > + dc->realize = gicv3_arm_its_realize;
> > + device_class_set_props(dc, gicv3_its_props);
> > + device_class_set_parent_reset(dc, gicv3_its_reset, &ic-
> > >parent_reset);
> > +}
> > +
> > +static const TypeInfo gicv3_its_info = {
> > + .name = TYPE_ARM_GICV3_ITS,
> > + .parent = TYPE_ARM_GICV3_ITS_COMMON,
> > + .instance_size = sizeof(GICv3ITSState),
> > + .class_init = gicv3_its_class_init,
> > + .class_size = sizeof(GICv3ITSClass),
> > +};
> > +
> > +static void gicv3_its_register_types(void)
> > +{
> > + type_register_static(&gicv3_its_info);
> > +}
> > +
> > +type_init(gicv3_its_register_types)
> > diff --git a/hw/intc/arm_gicv3_its_common.c
> > b/hw/intc/arm_gicv3_its_common.c
> > index 66c4c6a188..7d7f3882e7 100644
> > --- a/hw/intc/arm_gicv3_its_common.c
> > +++ b/hw/intc/arm_gicv3_its_common.c
> > @@ -50,6 +50,8 @@ static int gicv3_its_post_load(void *opaque, int
> > version_id)
> >
> > static const VMStateDescription vmstate_its = {
> > .name = "arm_gicv3_its",
> > + .version_id = 1,
> > + .minimum_version_id = 1,
> > .pre_save = gicv3_its_pre_save,
> > .post_load = gicv3_its_post_load,
> > .priority = MIG_PRI_GICV3_ITS,
> > @@ -99,14 +101,15 @@ static const MemoryRegionOps
> > gicv3_its_trans_ops = {
> > .endianness = DEVICE_NATIVE_ENDIAN,
> > };
> >
> > -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps
> > *ops)
> > +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps
> > *ops,
> > + const MemoryRegionOps *tops)
> > {
> > SysBusDevice *sbd = SYS_BUS_DEVICE(s);
> >
> > memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
> > "control", ITS_CONTROL_SIZE);
> > memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
> > - &gicv3_its_trans_ops, s,
> > + tops ? tops : &gicv3_its_trans_ops, s,
> > "translation", ITS_TRANS_SIZE);
> >
> > /* Our two regions are always adjacent, therefore we now
> > combine them
> > diff --git a/hw/intc/arm_gicv3_its_kvm.c
> > b/hw/intc/arm_gicv3_its_kvm.c
> > index b554d2ede0..0b4cbed28b 100644
> > --- a/hw/intc/arm_gicv3_its_kvm.c
> > +++ b/hw/intc/arm_gicv3_its_kvm.c
> > @@ -106,7 +106,7 @@ static void kvm_arm_its_realize(DeviceState
> > *dev, Error **errp)
> > kvm_arm_register_device(&s->iomem_its_cntrl, -1,
> > KVM_DEV_ARM_VGIC_GRP_ADDR,
> > KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0);
> >
> > - gicv3_its_init_mmio(s, NULL);
> > + gicv3_its_init_mmio(s, NULL, NULL);
> >
> > if (!kvm_device_check_attr(s->dev_fd,
> > KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
> > GITS_CTLR)) {
> > diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
> > index 05303a55c8..e0b06930a7 100644
> > --- a/hw/intc/gicv3_internal.h
> > +++ b/hw/intc/gicv3_internal.h
> > @@ -24,6 +24,7 @@
> > #ifndef QEMU_ARM_GICV3_INTERNAL_H
> > #define QEMU_ARM_GICV3_INTERNAL_H
> >
> > +#include "hw/registerfields.h"
> > #include "hw/intc/arm_gicv3_common.h"
> >
> > /* Distributor registers, as offsets from the distributor base
> > address */
> > @@ -67,6 +68,9 @@
> > #define GICD_CTLR_E1NWF (1U << 7)
> > #define GICD_CTLR_RWP (1U << 31)
> >
> > +/* 16 bits EventId */
> > +#define GICD_TYPER_IDBITS 0xf
> > +
> > /*
> > * Redistributor frame offsets from RD_base
> > */
> > @@ -122,18 +126,6 @@
> > #define GICR_WAKER_ProcessorSleep (1U << 1)
> > #define GICR_WAKER_ChildrenAsleep (1U << 2)
> >
> > -#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
> > -#define GICR_PROPBASER_ADDR_MASK (0xfffffffffULL <<
> > 12)
> > -#define GICR_PROPBASER_SHAREABILITY_MASK (3U << 10)
> > -#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
> > -#define GICR_PROPBASER_IDBITS_MASK (0x1f)
> > -
> > -#define GICR_PENDBASER_PTZ (1ULL << 62)
> > -#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
> > -#define GICR_PENDBASER_ADDR_MASK (0xffffffffULL <<
> > 16)
> > -#define GICR_PENDBASER_SHAREABILITY_MASK (3U << 10)
> > -#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
> > -
> > #define ICC_CTLR_EL1_CBPR (1U << 0)
> > #define ICC_CTLR_EL1_EOIMODE (1U << 1)
> > #define ICC_CTLR_EL1_PMHE (1U << 6)
> > @@ -239,6 +231,78 @@
> > #define ICH_VTR_EL2_PREBITS_SHIFT 26
> > #define ICH_VTR_EL2_PRIBITS_SHIFT 29
> >
> > +/* ITS Registers */
> > +
> > +FIELD(GITS_BASER, SIZE, 0, 8)
> > +FIELD(GITS_BASER, PAGESIZE, 8, 2)
> > +FIELD(GITS_BASER, SHAREABILITY, 10, 2)
> > +FIELD(GITS_BASER, PHYADDR, 12, 36)
> > +FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
> > +FIELD(GITS_BASER, PHYADDRH_64K, 48, 4)
> > +FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
> > +FIELD(GITS_BASER, OUTERCACHE, 53, 3)
> > +FIELD(GITS_BASER, TYPE, 56, 3)
> > +FIELD(GITS_BASER, INNERCACHE, 59, 3)
> > +FIELD(GITS_BASER, INDIRECT, 62, 1)
> > +FIELD(GITS_BASER, VALID, 63, 1)
> > +
> > +FIELD(GITS_CTLR, QUIESCENT, 31, 1)
> > +
> > +FIELD(GITS_TYPER, PHYSICAL, 0, 1)
> > +FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4)
> > +FIELD(GITS_TYPER, IDBITS, 8, 5)
> > +FIELD(GITS_TYPER, DEVBITS, 13, 5)
> > +FIELD(GITS_TYPER, SEIS, 18, 1)
> > +FIELD(GITS_TYPER, PTA, 19, 1)
> > +FIELD(GITS_TYPER, CIDBITS, 32, 4)
> > +FIELD(GITS_TYPER, CIL, 36, 1)
> > +
> > +#define GITS_BASER_PAGESIZE_4K 0
> > +#define GITS_BASER_PAGESIZE_16K 1
> > +#define GITS_BASER_PAGESIZE_64K 2
> > +
> > +#define GITS_ITT_TYPE_DEVICE 1ULL
> > +#define GITS_ITT_TYPE_COLLECTION 4ULL
> > +
> > +/**
> > + * Default features advertised by this version of ITS
> > + */
> > +/* Physical LPIs supported */
> > +#define GITS_TYPE_PHYSICAL (1U << 0)
> > +
> > +/*
> > + * 12 bytes Interrupt translation Table Entry size
> > + * ITE Lower 8 Bytes
> > + * Valid = 1 bit,InterruptType = 1 bit,
> > + * Size of LPI number space[considering max 24 bits],
> > + * Size of LPI number space[considering max 24 bits],
> > + * ITE Higher 4 Bytes
> > + * ICID = 16 bits,
> > + * vPEID = 16 bits
> > + */
> > +#define ITS_ITT_ENTRY_SIZE 0xC
> > +
> > +/* 16 bits EventId */
> > +#define ITS_IDBITS GICD_TYPER_IDBITS
> > +
> > +/* 16 bits DeviceId */
> > +#define ITS_DEVBITS 0xF
> > +
> > +/* 16 bits CollectionId */
> > +#define ITS_CIDBITS 0xF
> > +
> > +/*
> > + * 8 bytes Device Table Entry size
> > + * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits
> > + */
> > +#define GITS_DTE_SIZE (0x8ULL)
> > +
> > +/*
> > + * 8 bytes Collection Table Entry size
> > + * Valid = 1 bit,RDBase = 36 bits(considering max RDBASE)
> > + */
> > +#define GITS_CTE_SIZE (0x8ULL)
> > +
> > /* Special interrupt IDs */
> > #define INTID_SECURE 1020
> > #define INTID_NONSECURE 1021
> > diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> > index 6e52a166e3..4dcfea6aa8 100644
> > --- a/hw/intc/meson.build
> > +++ b/hw/intc/meson.build
> > @@ -8,6 +8,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true:
> > files(
> > 'arm_gicv3_dist.c',
> > 'arm_gicv3_its_common.c',
> > 'arm_gicv3_redist.c',
> > + 'arm_gicv3_its.c',
> > ))
> > softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true:
> > files('etraxfs_pic.c'))
> > softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true:
> > files('heathrow_pic.c'))
> > diff --git a/include/hw/intc/arm_gicv3_its_common.h
> > b/include/hw/intc/arm_gicv3_its_common.h
> > index 5a0952b404..65d1191db1 100644
> > --- a/include/hw/intc/arm_gicv3_its_common.h
> > +++ b/include/hw/intc/arm_gicv3_its_common.h
> > @@ -25,17 +25,22 @@
> > #include "hw/intc/arm_gicv3_common.h"
> > #include "qom/object.h"
> >
> > +#define TYPE_ARM_GICV3_ITS "arm-gicv3-its"
> > +
> > #define ITS_CONTROL_SIZE 0x10000
> > #define ITS_TRANS_SIZE 0x10000
> > #define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
> >
> > #define GITS_CTLR 0x0
> > #define GITS_IIDR 0x4
> > +#define GITS_TYPER 0x8
> > #define GITS_CBASER 0x80
> > #define GITS_CWRITER 0x88
> > #define GITS_CREADR 0x90
> > #define GITS_BASER 0x100
> >
> > +#define GITS_TRANSLATER 0x0040
> > +
> > struct GICv3ITSState {
> > SysBusDevice parent_obj;
> >
> > @@ -52,6 +57,7 @@ struct GICv3ITSState {
> > /* Registers */
> > uint32_t ctlr;
> > uint32_t iidr;
> > + uint64_t typer;
> > uint64_t cbaser;
> > uint64_t cwriter;
> > uint64_t creadr;
> > @@ -62,7 +68,8 @@ struct GICv3ITSState {
> >
> > typedef struct GICv3ITSState GICv3ITSState;
> >
> > -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps
> > *ops);
> > +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps
> > *ops,
> > + const MemoryRegionOps *tops);
> >
> > #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
> > typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
> >
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
2021-07-06 13:27 ` Peter Maydell
@ 2021-07-07 2:08 ` shashi.mallela
0 siblings, 0 replies; 41+ messages in thread
From: shashi.mallela @ 2021-07-07 2:08 UTC (permalink / raw)
To: Peter Maydell
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Tue, 2021-07-06 at 14:27 +0100, Peter Maydell wrote:
> On Tue, 6 Jul 2021 at 13:46, <shashi.mallela@linaro.org> wrote:
> > On Tue, 2021-07-06 at 10:19 +0100, Peter Maydell wrote:
> > > On Tue, 6 Jul 2021 at 04:25, <shashi.mallela@linaro.org> wrote:
> > >
> > > But the pseudocode for MAPTI does not say anywhere that we should
> > > be checking the pIntID against any CPU's GICR_PROPBASER field.
> > > It is checked only by the checks in LPIOutOfRange(), which tests:
> > > * is it larger than permitted by GICD_TYPER.IDbits
> > > * is it not in the LPI range and not 1023
> > >
> > > Checking whether the intID is too big and would cause us to index
> > > off the end of the redistributor's configuration table should be
> > > done
> > > later, only when the ITS actually sends the interrupt to a
> > > particular
> > > redistributor, I think.
> > >
> > > (You can't rely on the guest having done the MAPC before the
> > > MAPTI;
> > > and in any case the guest could choose to do a MAPC to a
> > > different
> > > redistributor after it's done the MAPTI.)
> > We already have the "intID too big check" in place within the
> > redistributor processing when ITS sends the interrupt trigger.
> > "the LPI range and not 1023" is also handled in this function,but
> > for
> > validating "is it larger than permitted by GICD_TYPER.IDbits",the
> > source of GICD_TYPER.IDbits is GICR_PROPBASER because we pick up
> > min of
> > GICR_PROPBASER.IDbits and GICD_TYPER.IDBits.
> >
> > If we are to not use gicr_propbaser,then are we good to just accept
> > the
> > intID value here since we are validating the same during interrupt
> > processing?
>
> You should check the things the pseudocode says you should check.
> When processing MAPTI, that's GICD_TYPER.IDbits.
> GICR_PROPBASER.IDbits
> is not the same thing because the guest can set it to a smaller
> value.
Have made changes in code to check "intID too big" case using
GICD_TYPER.IDbits instead of GICR_PROPBASER.IDbits
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
2021-07-05 18:58 ` Peter Maydell
@ 2021-07-07 2:08 ` shashi.mallela
0 siblings, 0 replies; 41+ messages in thread
From: shashi.mallela @ 2021-07-07 2:08 UTC (permalink / raw)
To: Peter Maydell
Cc: Michael S. Tsirkin, Radoslaw Biernacki, QEMU Developers,
qemu-arm, Igor Mammedov, Leif Lindholm
On Mon, 2021-07-05 at 19:58 +0100, Peter Maydell wrote:
> On Mon, 5 Jul 2021 at 18:04, <shashi.mallela@linaro.org> wrote:
> > On Mon, 2021-07-05 at 17:25 +0100, Peter Maydell wrote:
> > > On Mon, 5 Jul 2021 at 16:55, <shashi.mallela@linaro.org> wrote:
> > > > On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> > > > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > > > > shashi.mallela@linaro.org> wrote:
> > > > > > Added register definitions relevant to ITS,implemented
> > > > > > overall
> > > > > > ITS device framework with stubs for ITS control and
> > > > > > translater
> > > > > > regions read/write,extended ITS common to handle mmio init
> > > > > > between
> > > > > > existing kvm device and newer qemu device.
> > > > > >
> > > > > > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > > > > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> > > > > > +static void gicv3_arm_its_realize(DeviceState *dev, Error
> > > > > > **errp)
> > > > > > +{
> > > > > > + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > > > > > +
> > > > > > + gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > > > > > &gicv3_its_translation_ops);
> > > > > > +
> > > > > > + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> > > > >
> > > > > Can you remind me why we make this check, please? When would
> > > > > we
> > > > > have created an ITS device but not have a GICv3 with LPI
> > > > > support?
> > > > This check applies to GIC's physical LPI support only as
> > > > against
> > > > GIC's
> > > > virtual LPI support.
> > >
> > > Right, but when would we have a GIC with no physical LPI support
> > > but an ITS is present ?
> > If we only support Direct injection of virtual interrupts (which
> > can
> > have their own vPEID and the vPE table),then the ITS present could
> > havejust virtual LPI support
>
> This patchset does not support a virtual-LPI-only ITS, though:
> it doesn't support virtual LPIs at all.
> If you use it with CPUs without physical LPI support , this code will
> skip
> entirely setting GITS_TYPER and will make reset do nothing, and then
> the
> rest of the ITS implementation will misbehave.
>
> I think what we should do is:
> * in realize, check every CPU to make sure its redistributor
> supports physical LPIs, and return an error from realize if not
> * in reset, don't check anything
Done
>
> If we add virtual-LPI-only ITS support later, we can always update
> this code appropriately.
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added
2021-07-06 9:29 ` Eric Auger
@ 2021-07-08 17:27 ` Eric Auger
2021-08-05 21:14 ` shashi.mallela
0 siblings, 1 reply; 41+ messages in thread
From: Eric Auger @ 2021-07-08 17:27 UTC (permalink / raw)
To: Shashi Mallela, peter.maydell, leif, rad, mst, imammedo
Cc: qemu-arm, qemu-devel
Hi Shashi,
On 7/6/21 11:29 AM, Eric Auger wrote:
> Hi,
>
> On 6/30/21 5:31 PM, Shashi Mallela wrote:
>> Defined descriptors for ITS device table,collection table and ITS
>> command queue entities.Implemented register read/write functions,
>> extract ITS table parameters and command queue parameters,extended
>> gicv3 common to capture qemu address space(which host the ITS table
>> platform memories required for subsequent ITS processing) and
>> initialize the same in ITS device.
>>
>> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>> hw/intc/arm_gicv3_its.c | 376 +++++++++++++++++++++++++
>> hw/intc/gicv3_internal.h | 31 +-
>> include/hw/intc/arm_gicv3_common.h | 3 +
>> include/hw/intc/arm_gicv3_its_common.h | 23 ++
>> 4 files changed, 432 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
>> index 545cda3665..2d786a1e21 100644
>> --- a/hw/intc/arm_gicv3_its.c
>> +++ b/hw/intc/arm_gicv3_its.c
>> @@ -28,6 +28,160 @@ struct GICv3ITSClass {
>> void (*parent_reset)(DeviceState *dev);
>> };
>>
>> +static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
>> +{
>> + uint64_t result = 0;
>> +
>> + switch (page_sz) {
>> + case GITS_PAGE_SIZE_4K:
>> + case GITS_PAGE_SIZE_16K:
>> + result = FIELD_EX64(value, GITS_BASER, PHYADDR);
> << 12 ?
Did you check that? Seems unchanged in v6?
Thanks
Eric
>> + break;
>> +
>> + case GITS_PAGE_SIZE_64K:
>> + result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16;
>> + result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48;
>> + break;
>> +
>> + default:
>> + break;
>> + }
>> + return result;
>> +}
>> +
>> +/*
>> + * This function extracts the ITS Device and Collection table specific
>> + * parameters (like base_addr, size etc) from GITS_BASER register.
>> + * It is called during ITS enable and also during post_load migration
>> + */
>> +static void extract_table_params(GICv3ITSState *s)
>> +{
>> + uint16_t num_pages = 0;
>> + uint8_t page_sz_type;
>> + uint8_t type;
>> + uint32_t page_sz = 0;
>> + uint64_t value;
>> +
>> + for (int i = 0; i < 8; i++) {
>> + value = s->baser[i];
>> +
>> + if (!value) {
>> + continue;
>> + }
>> +
>> + page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
>> +
>> + switch (page_sz_type) {
>> + case 0:
>> + page_sz = GITS_PAGE_SIZE_4K;
>> + break;
>> +
>> + case 1:
>> + page_sz = GITS_PAGE_SIZE_16K;
>> + break;
>> +
>> + case 2:
>> + case 3:
>> + page_sz = GITS_PAGE_SIZE_64K;
>> + break;
>> +
>> + default:
>> + g_assert_not_reached();
>> + }
>> +
>> + num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
>> +
>> + type = FIELD_EX64(value, GITS_BASER, TYPE);
>> +
>> + switch (type) {
>> +
>> + case GITS_ITT_TYPE_DEVICE:
>> + memset(&s->dt, 0 , sizeof(s->dt));
>> + s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
>> +
>> + if (!s->dt.valid) {
>> + return;
>> + }
>> +
>> + s->dt.page_sz = page_sz;
>> + s->dt.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
>> + s->dt.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
>> +
>> + if (!s->dt.indirect) {
>> + s->dt.max_entries = (num_pages * page_sz) / s->dt.entry_sz;
>> + } else {
>> + s->dt.max_entries = (((num_pages * page_sz) /
>> + L1TABLE_ENTRY_SIZE) *
>> + (page_sz / s->dt.entry_sz));
>> + }
>> +
>> + s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s->typer, GITS_TYPER,
>> + DEVBITS) + 1));
>> +
>> + s->dt.base_addr = baser_base_addr(value, page_sz);
>> +
>> + break;
>> +
>> + case GITS_ITT_TYPE_COLLECTION:
>> + memset(&s->ct, 0 , sizeof(s->ct));
>> + s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
>> +
>> + /*
>> + * GITS_TYPER.HCC is 0 for this implementation
>> + * hence writes are discarded if ct.valid is 0
>> + */
>> + if (!s->ct.valid) {
>> + return;
>> + }
>> +
>> + s->ct.page_sz = page_sz;
>> + s->ct.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
>> + s->ct.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
>> +
>> + if (!s->ct.indirect) {
>> + s->ct.max_entries = (num_pages * page_sz) / s->ct.entry_sz;
>> + } else {
>> + s->ct.max_entries = (((num_pages * page_sz) /
>> + L1TABLE_ENTRY_SIZE) *
>> + (page_sz / s->ct.entry_sz));
>> + }
>> +
>> + if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
>> + s->ct.maxids.max_collids = (1UL << (FIELD_EX64(s->typer,
>> + GITS_TYPER, CIDBITS) + 1));
>> + } else {
>> + /* 16-bit CollectionId supported when CIL == 0 */
>> + s->ct.maxids.max_collids = (1UL << 16);
>> + }
>> +
>> + s->ct.base_addr = baser_base_addr(value, page_sz);
>> +
>> + break;
>> +
>> + default:
>> + break;
>> + }
>> + }
>> +}
>> +
>> +static void extract_cmdq_params(GICv3ITSState *s)
>> +{
>> + uint16_t num_pages = 0;
>> + uint64_t value = s->cbaser;
>> +
>> + num_pages = FIELD_EX64(value, GITS_CBASER, SIZE) + 1;
>> +
>> + memset(&s->cq, 0 , sizeof(s->cq));
>> + s->cq.valid = FIELD_EX64(value, GITS_CBASER, VALID);
>> +
>> + if (s->cq.valid) {
>> + s->cq.max_entries = (num_pages * GITS_PAGE_SIZE_4K) /
>> + GITS_CMDQ_ENTRY_SIZE;
>> + s->cq.base_addr = FIELD_EX64(value, GITS_CBASER, PHYADDR);
>> + s->cq.base_addr <<= R_GITS_CBASER_PHYADDR_SHIFT;
>> + }
>> +}
>> +
>> static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
>> uint64_t data, unsigned size,
>> MemTxAttrs attrs)
>> @@ -41,7 +195,99 @@ static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
>> uint64_t value, MemTxAttrs attrs)
>> {
>> MemTxResult result = MEMTX_OK;
>> + int index;
>>
>> + switch (offset) {
>> + case GITS_CTLR:
>> + s->ctlr |= (value & ~(s->ctlr));
>> +
>> + if (s->ctlr & ITS_CTLR_ENABLED) {
>> + extract_table_params(s);
>> + extract_cmdq_params(s);
>> + s->creadr = 0;
>> + }
>> + break;
>> + case GITS_CBASER:
>> + /*
>> + * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
>> + * already enabled
>> + */
>> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
>> + s->cbaser = deposit64(s->cbaser, 0, 32, value);
>> + s->creadr = 0;
>> + s->cwriter = s->creadr;
>> + }
>> + break;
>> + case GITS_CBASER + 4:
>> + /*
>> + * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
>> + * already enabled
>> + */
>> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
>> + s->cbaser = deposit64(s->cbaser, 32, 32, value);
>> + s->creadr = 0;
>> + s->cwriter = s->creadr;
>> + }
>> + break;
>> + case GITS_CWRITER:
>> + s->cwriter = deposit64(s->cwriter, 0, 32,
>> + (value & ~R_GITS_CWRITER_RETRY_MASK));
>> + break;
>> + case GITS_CWRITER + 4:
>> + s->cwriter = deposit64(s->cwriter, 32, 32, value);
>> + break;
>> + case GITS_CREADR:
>> + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
>> + s->creadr = deposit64(s->creadr, 0, 32,
>> + (value & ~R_GITS_CREADR_STALLED_MASK));
>> + } else {
>> + /* RO register, ignore the write */
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: invalid guest write to RO register at offset "
>> + TARGET_FMT_plx "\n", __func__, offset);
>> + }
>> + break;
>> + case GITS_CREADR + 4:
>> + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
>> + s->creadr = deposit64(s->creadr, 32, 32, value);
>> + } else {
>> + /* RO register, ignore the write */
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: invalid guest write to RO register at offset "
>> + TARGET_FMT_plx "\n", __func__, offset);
>> + }
>> + break;
>> + case GITS_BASER ... GITS_BASER + 0x3f:
>> + /*
>> + * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is
>> + * already enabled
>> + */
>> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
>> + index = (offset - GITS_BASER) / 8;
>> +
>> + if (offset & 7) {
>> + value <<= 32;
>> + value &= ~GITS_BASER_RO_MASK;
>> + s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(0, 32);
>> + s->baser[index] |= value;
>> + } else {
>> + value &= ~GITS_BASER_RO_MASK;
>> + s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(32, 32);
>> + s->baser[index] |= value;
>> + }
>> + }
>> + break;
>> + case GITS_IIDR:
>> + case GITS_IDREGS ... GITS_IDREGS + 0x2f:
>> + /* RO registers, ignore the write */
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: invalid guest write to RO register at offset "
>> + TARGET_FMT_plx "\n", __func__, offset);
>> + break;
>> + default:
>> + result = MEMTX_ERROR;
>> + break;
>> + }
>> return result;
>> }
>>
>> @@ -49,7 +295,55 @@ static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
>> uint64_t *data, MemTxAttrs attrs)
>> {
>> MemTxResult result = MEMTX_OK;
>> + int index;
>>
>> + switch (offset) {
>> + case GITS_CTLR:
>> + *data = s->ctlr;
>> + break;
>> + case GITS_IIDR:
>> + *data = gicv3_iidr();
>> + break;
>> + case GITS_IDREGS ... GITS_IDREGS + 0x2f:
>> + /* ID registers */
>> + *data = gicv3_idreg(offset - GITS_IDREGS);
>> + break;
>> + case GITS_TYPER:
>> + *data = extract64(s->typer, 0, 32);
>> + break;
>> + case GITS_TYPER + 4:
>> + *data = extract64(s->typer, 32, 32);
>> + break;
>> + case GITS_CBASER:
>> + *data = extract64(s->cbaser, 0, 32);
>> + break;
>> + case GITS_CBASER + 4:
>> + *data = extract64(s->cbaser, 32, 32);
>> + break;
>> + case GITS_CREADR:
>> + *data = extract64(s->creadr, 0, 32);
>> + break;
>> + case GITS_CREADR + 4:
>> + *data = extract64(s->creadr, 32, 32);
>> + break;
>> + case GITS_CWRITER:
>> + *data = extract64(s->cwriter, 0, 32);
>> + break;
>> + case GITS_CWRITER + 4:
>> + *data = extract64(s->cwriter, 32, 32);
>> + break;
>> + case GITS_BASER ... GITS_BASER + 0x3f:
>> + index = (offset - GITS_BASER) / 8;
>> + if (offset & 7) {
>> + *data = extract64(s->baser[index], 32, 32);
>> + } else {
>> + *data = extract64(s->baser[index], 0, 32);
>> + }
>> + break;
>> + default:
>> + result = MEMTX_ERROR;
>> + break;
>> + }
>> return result;
>> }
>>
>> @@ -57,7 +351,54 @@ static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
>> uint64_t value, MemTxAttrs attrs)
>> {
>> MemTxResult result = MEMTX_OK;
>> + int index;
>>
>> + switch (offset) {
>> + case GITS_BASER ... GITS_BASER + 0x3f:
>> + /*
>> + * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is
>> + * already enabled
>> + */
>> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
>> + index = (offset - GITS_BASER) / 8;
>> + s->baser[index] &= GITS_BASER_RO_MASK;
>> + s->baser[index] |= (value & ~GITS_BASER_RO_MASK);
>> + }
>> + break;
>> + case GITS_CBASER:
>> + /*
>> + * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
>> + * already enabled
>> + */
>> + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
>> + s->cbaser = value;
>> + s->creadr = 0;
>> + s->cwriter = s->creadr;
>> + }
>> + break;
>> + case GITS_CWRITER:
>> + s->cwriter = value & ~R_GITS_CWRITER_RETRY_MASK;
>> + break;
>> + case GITS_CREADR:
>> + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
>> + s->creadr = value & ~R_GITS_CREADR_STALLED_MASK;
>> + } else {
>> + /* RO register, ignore the write */
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: invalid guest write to RO register at offset "
>> + TARGET_FMT_plx "\n", __func__, offset);
>> + }
>> + break;
>> + case GITS_TYPER:
>> + /* RO registers, ignore the write */
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: invalid guest write to RO register at offset "
>> + TARGET_FMT_plx "\n", __func__, offset);
>> + break;
>> + default:
>> + result = MEMTX_ERROR;
>> + break;
>> + }
>> return result;
>> }
>>
>> @@ -65,7 +406,29 @@ static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
>> uint64_t *data, MemTxAttrs attrs)
>> {
>> MemTxResult result = MEMTX_OK;
>> + int index;
>>
>> + switch (offset) {
>> + case GITS_TYPER:
>> + *data = s->typer;
>> + break;
>> + case GITS_BASER ... GITS_BASER + 0x3f:
>> + index = (offset - GITS_BASER) / 8;
>> + *data = s->baser[index];
>> + break;
>> + case GITS_CBASER:
>> + *data = s->cbaser;
>> + break;
>> + case GITS_CREADR:
>> + *data = s->creadr;
>> + break;
>> + case GITS_CWRITER:
>> + *data = s->cwriter;
>> + break;
>> + default:
>> + result = MEMTX_ERROR;
>> + break;
>> + }
>> return result;
>> }
>>
>> @@ -162,6 +525,9 @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
>> gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops);
>>
>> if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
>> + address_space_init(&s->gicv3->dma_as, s->gicv3->dma,
>> + "gicv3-its-sysmem");
>> +
>> /* set the ITS default features supported */
>> s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
>> GITS_TYPE_PHYSICAL);
>> @@ -208,6 +574,14 @@ static void gicv3_its_reset(DeviceState *dev)
>> }
>> }
>>
>> +static void gicv3_its_post_load(GICv3ITSState *s)
>> +{
>> + if (s->ctlr & ITS_CTLR_ENABLED) {
>> + extract_table_params(s);
>> + extract_cmdq_params(s);
>> + }
>> +}
>> +
>> static Property gicv3_its_props[] = {
>> DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3",
>> GICv3State *),
>> @@ -218,10 +592,12 @@ static void gicv3_its_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
>> + GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
>>
>> dc->realize = gicv3_arm_its_realize;
>> device_class_set_props(dc, gicv3_its_props);
>> device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
>> + icc->post_load = gicv3_its_post_load;
>> }
>>
>> static const TypeInfo gicv3_its_info = {
>> diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
>> index e0b06930a7..dc2c1bc45b 100644
>> --- a/hw/intc/gicv3_internal.h
>> +++ b/hw/intc/gicv3_internal.h
>> @@ -238,7 +238,7 @@ FIELD(GITS_BASER, PAGESIZE, 8, 2)
>> FIELD(GITS_BASER, SHAREABILITY, 10, 2)
>> FIELD(GITS_BASER, PHYADDR, 12, 36)
>> FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
>> -FIELD(GITS_BASER, PHYADDRH_64K, 48, 4)
>> +FIELD(GITS_BASER, PHYADDRH_64K, 12, 4)
> should have been addressed earlier
>> FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
>> FIELD(GITS_BASER, OUTERCACHE, 53, 3)
>> FIELD(GITS_BASER, TYPE, 56, 3)
>> @@ -246,6 +246,20 @@ FIELD(GITS_BASER, INNERCACHE, 59, 3)
>> FIELD(GITS_BASER, INDIRECT, 62, 1)
>> FIELD(GITS_BASER, VALID, 63, 1)
>>
>> +FIELD(GITS_CBASER, SIZE, 0, 8)
>> +FIELD(GITS_CBASER, SHAREABILITY, 10, 2)
>> +FIELD(GITS_CBASER, PHYADDR, 12, 40)
>> +FIELD(GITS_CBASER, OUTERCACHE, 53, 3)
>> +FIELD(GITS_CBASER, INNERCACHE, 59, 3)
>> +FIELD(GITS_CBASER, VALID, 63, 1)
>> +
>> +FIELD(GITS_CREADR, STALLED, 0, 1)
>> +FIELD(GITS_CREADR, OFFSET, 5, 15)
>> +
>> +FIELD(GITS_CWRITER, RETRY, 0, 1)
>> +FIELD(GITS_CWRITER, OFFSET, 5, 15)
>> +
>> +FIELD(GITS_CTLR, ENABLED, 0, 1)
>> FIELD(GITS_CTLR, QUIESCENT, 31, 1)
>>
>> FIELD(GITS_TYPER, PHYSICAL, 0, 1)
>> @@ -257,6 +271,13 @@ FIELD(GITS_TYPER, PTA, 19, 1)
>> FIELD(GITS_TYPER, CIDBITS, 32, 4)
>> FIELD(GITS_TYPER, CIL, 36, 1)
>>
>> +#define GITS_IDREGS 0xFFD0
>> +
>> +#define ITS_CTLR_ENABLED (1U) /* ITS Enabled */
>> +
>> +#define GITS_BASER_RO_MASK (R_GITS_BASER_ENTRYSIZE_MASK | \
>> + R_GITS_BASER_TYPE_MASK)
>> +
>> #define GITS_BASER_PAGESIZE_4K 0
>> #define GITS_BASER_PAGESIZE_16K 1
>> #define GITS_BASER_PAGESIZE_64K 2
>> @@ -264,6 +285,14 @@ FIELD(GITS_TYPER, CIL, 36, 1)
>> #define GITS_ITT_TYPE_DEVICE 1ULL
>> #define GITS_ITT_TYPE_COLLECTION 4ULL
>>
>> +#define GITS_PAGE_SIZE_4K 0x1000
>> +#define GITS_PAGE_SIZE_16K 0x4000
>> +#define GITS_PAGE_SIZE_64K 0x10000
>> +
>> +#define L1TABLE_ENTRY_SIZE 8
>> +
>> +#define GITS_CMDQ_ENTRY_SIZE 32
>> +
>> /**
>> * Default features advertised by this version of ITS
>> */
>> diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
>> index 91491a2f66..1fd5cedbbd 100644
>> --- a/include/hw/intc/arm_gicv3_common.h
>> +++ b/include/hw/intc/arm_gicv3_common.h
>> @@ -226,6 +226,9 @@ struct GICv3State {
>> int dev_fd; /* kvm device fd if backed by kvm vgic support */
>> Error *migration_blocker;
>>
>> + MemoryRegion *dma;
>> + AddressSpace dma_as;
>> +
>> /* Distributor */
>>
>> /* for a GIC with the security extensions the NS banked version of this
>> diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
>> index 65d1191db1..4e79145dde 100644
>> --- a/include/hw/intc/arm_gicv3_its_common.h
>> +++ b/include/hw/intc/arm_gicv3_its_common.h
>> @@ -41,6 +41,25 @@
>>
>> #define GITS_TRANSLATER 0x0040
>>
>> +typedef struct {
>> + bool valid;
>> + bool indirect;
>> + uint16_t entry_sz;
>> + uint32_t page_sz;
>> + uint32_t max_entries;
>> + union {
>> + uint32_t max_devids;
>> + uint32_t max_collids;
>> + } maxids;
>> + uint64_t base_addr;
>> +} TableDesc;
>> +
>> +typedef struct {
>> + bool valid;
>> + uint32_t max_entries;
>> + uint64_t base_addr;
>> +} CmdQDesc;
>> +
>> struct GICv3ITSState {
>> SysBusDevice parent_obj;
>>
>> @@ -63,6 +82,10 @@ struct GICv3ITSState {
>> uint64_t creadr;
>> uint64_t baser[8];
>>
>> + TableDesc dt;
>> + TableDesc ct;
>> + CmdQDesc cq;
>> +
>> Error *migration_blocker;
>> };
>>
>>
> Besides
> Reviewed-by: Eric Auger <eric.auger@redhat.com>
>
> Eric
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added
2021-07-08 17:27 ` Eric Auger
@ 2021-08-05 21:14 ` shashi.mallela
0 siblings, 0 replies; 41+ messages in thread
From: shashi.mallela @ 2021-08-05 21:14 UTC (permalink / raw)
To: Eric Auger, peter.maydell, leif, rad, mst, imammedo; +Cc: qemu-arm, qemu-devel
On Thu, 2021-07-08 at 19:27 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 7/6/21 11:29 AM, Eric Auger wrote:
> > Hi,
> >
> > On 6/30/21 5:31 PM, Shashi Mallela wrote:
> > > Defined descriptors for ITS device table,collection table and ITS
> > > command queue entities.Implemented register read/write functions,
> > > extract ITS table parameters and command queue
> > > parameters,extended
> > > gicv3 common to capture qemu address space(which host the ITS
> > > table
> > > platform memories required for subsequent ITS processing) and
> > > initialize the same in ITS device.
> > >
> > > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> > > ---
> > > hw/intc/arm_gicv3_its.c | 376
> > > +++++++++++++++++++++++++
> > > hw/intc/gicv3_internal.h | 31 +-
> > > include/hw/intc/arm_gicv3_common.h | 3 +
> > > include/hw/intc/arm_gicv3_its_common.h | 23 ++
> > > 4 files changed, 432 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > > index 545cda3665..2d786a1e21 100644
> > > --- a/hw/intc/arm_gicv3_its.c
> > > +++ b/hw/intc/arm_gicv3_its.c
> > > @@ -28,6 +28,160 @@ struct GICv3ITSClass {
> > > void (*parent_reset)(DeviceState *dev);
> > > };
> > >
> > > +static uint64_t baser_base_addr(uint64_t value, uint32_t
> > > page_sz)
> > > +{
> > > + uint64_t result = 0;
> > > +
> > > + switch (page_sz) {
> > > + case GITS_PAGE_SIZE_4K:
> > > + case GITS_PAGE_SIZE_16K:
> > > + result = FIELD_EX64(value, GITS_BASER, PHYADDR);
> > << 12 ?
> Did you check that? Seems unchanged in v6?
>
> Thanks
>
> Eric
Have taken care of it in the v7 patch
> > > + break;
> > > +
> > > + case GITS_PAGE_SIZE_64K:
> > > + result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) <<
> > > 16;
> > > + result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) <<
> > > 48;
> > > + break;
> > > +
> > > + default:
> > > + break;
> > > + }
> > > + return result;
> > > +}
> > > +
> > > +/*
> > > + * This function extracts the ITS Device and Collection table
> > > specific
> > > + * parameters (like base_addr, size etc) from GITS_BASER
> > > register.
> > > + * It is called during ITS enable and also during post_load
> > > migration
> > > + */
> > > +static void extract_table_params(GICv3ITSState *s)
> > > +{
> > > + uint16_t num_pages = 0;
> > > + uint8_t page_sz_type;
> > > + uint8_t type;
> > > + uint32_t page_sz = 0;
> > > + uint64_t value;
> > > +
> > > + for (int i = 0; i < 8; i++) {
> > > + value = s->baser[i];
> > > +
> > > + if (!value) {
> > > + continue;
> > > + }
> > > +
> > > + page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
> > > +
> > > + switch (page_sz_type) {
> > > + case 0:
> > > + page_sz = GITS_PAGE_SIZE_4K;
> > > + break;
> > > +
> > > + case 1:
> > > + page_sz = GITS_PAGE_SIZE_16K;
> > > + break;
> > > +
> > > + case 2:
> > > + case 3:
> > > + page_sz = GITS_PAGE_SIZE_64K;
> > > + break;
> > > +
> > > + default:
> > > + g_assert_not_reached();
> > > + }
> > > +
> > > + num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
> > > +
> > > + type = FIELD_EX64(value, GITS_BASER, TYPE);
> > > +
> > > + switch (type) {
> > > +
> > > + case GITS_ITT_TYPE_DEVICE:
> > > + memset(&s->dt, 0 , sizeof(s->dt));
> > > + s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
> > > +
> > > + if (!s->dt.valid) {
> > > + return;
> > > + }
> > > +
> > > + s->dt.page_sz = page_sz;
> > > + s->dt.indirect = FIELD_EX64(value, GITS_BASER,
> > > INDIRECT);
> > > + s->dt.entry_sz = FIELD_EX64(value, GITS_BASER,
> > > ENTRYSIZE);
> > > +
> > > + if (!s->dt.indirect) {
> > > + s->dt.max_entries = (num_pages * page_sz) / s-
> > > >dt.entry_sz;
> > > + } else {
> > > + s->dt.max_entries = (((num_pages * page_sz) /
> > > + L1TABLE_ENTRY_SIZE) *
> > > + (page_sz / s-
> > > >dt.entry_sz));
> > > + }
> > > +
> > > + s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s-
> > > >typer, GITS_TYPER,
> > > + DEVBITS) + 1));
> > > +
> > > + s->dt.base_addr = baser_base_addr(value, page_sz);
> > > +
> > > + break;
> > > +
> > > + case GITS_ITT_TYPE_COLLECTION:
> > > + memset(&s->ct, 0 , sizeof(s->ct));
> > > + s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
> > > +
> > > + /*
> > > + * GITS_TYPER.HCC is 0 for this implementation
> > > + * hence writes are discarded if ct.valid is 0
> > > + */
> > > + if (!s->ct.valid) {
> > > + return;
> > > + }
> > > +
> > > + s->ct.page_sz = page_sz;
> > > + s->ct.indirect = FIELD_EX64(value, GITS_BASER,
> > > INDIRECT);
> > > + s->ct.entry_sz = FIELD_EX64(value, GITS_BASER,
> > > ENTRYSIZE);
> > > +
> > > + if (!s->ct.indirect) {
> > > + s->ct.max_entries = (num_pages * page_sz) / s-
> > > >ct.entry_sz;
> > > + } else {
> > > + s->ct.max_entries = (((num_pages * page_sz) /
> > > + L1TABLE_ENTRY_SIZE) *
> > > + (page_sz / s-
> > > >ct.entry_sz));
> > > + }
> > > +
> > > + if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
> > > + s->ct.maxids.max_collids = (1UL <<
> > > (FIELD_EX64(s->typer,
> > > + GITS_TYPER, CIDBITS)
> > > + 1));
> > > + } else {
> > > + /* 16-bit CollectionId supported when CIL == 0
> > > */
> > > + s->ct.maxids.max_collids = (1UL << 16);
> > > + }
> > > +
> > > + s->ct.base_addr = baser_base_addr(value, page_sz);
> > > +
> > > + break;
> > > +
> > > + default:
> > > + break;
> > > + }
> > > + }
> > > +}
> > > +
> > > +static void extract_cmdq_params(GICv3ITSState *s)
> > > +{
> > > + uint16_t num_pages = 0;
> > > + uint64_t value = s->cbaser;
> > > +
> > > + num_pages = FIELD_EX64(value, GITS_CBASER, SIZE) + 1;
> > > +
> > > + memset(&s->cq, 0 , sizeof(s->cq));
> > > + s->cq.valid = FIELD_EX64(value, GITS_CBASER, VALID);
> > > +
> > > + if (s->cq.valid) {
> > > + s->cq.max_entries = (num_pages * GITS_PAGE_SIZE_4K) /
> > > + GITS_CMDQ_ENTRY_SIZE;
> > > + s->cq.base_addr = FIELD_EX64(value, GITS_CBASER,
> > > PHYADDR);
> > > + s->cq.base_addr <<= R_GITS_CBASER_PHYADDR_SHIFT;
> > > + }
> > > +}
> > > +
> > > static MemTxResult gicv3_its_translation_write(void *opaque,
> > > hwaddr offset,
> > > uint64_t data,
> > > unsigned size,
> > > MemTxAttrs attrs)
> > > @@ -41,7 +195,99 @@ static MemTxResult its_writel(GICv3ITSState
> > > *s, hwaddr offset,
> > > uint64_t value, MemTxAttrs attrs)
> > > {
> > > MemTxResult result = MEMTX_OK;
> > > + int index;
> > >
> > > + switch (offset) {
> > > + case GITS_CTLR:
> > > + s->ctlr |= (value & ~(s->ctlr));
> > > +
> > > + if (s->ctlr & ITS_CTLR_ENABLED) {
> > > + extract_table_params(s);
> > > + extract_cmdq_params(s);
> > > + s->creadr = 0;
> > > + }
> > > + break;
> > > + case GITS_CBASER:
> > > + /*
> > > + * IMPDEF choice:- GITS_CBASER register becomes RO if
> > > ITS is
> > > + * already enabled
> > > + */
> > > + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> > > + s->cbaser = deposit64(s->cbaser, 0, 32, value);
> > > + s->creadr = 0;
> > > + s->cwriter = s->creadr;
> > > + }
> > > + break;
> > > + case GITS_CBASER + 4:
> > > + /*
> > > + * IMPDEF choice:- GITS_CBASER register becomes RO if
> > > ITS is
> > > + * already enabled
> > > + */
> > > + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> > > + s->cbaser = deposit64(s->cbaser, 32, 32, value);
> > > + s->creadr = 0;
> > > + s->cwriter = s->creadr;
> > > + }
> > > + break;
> > > + case GITS_CWRITER:
> > > + s->cwriter = deposit64(s->cwriter, 0, 32,
> > > + (value &
> > > ~R_GITS_CWRITER_RETRY_MASK));
> > > + break;
> > > + case GITS_CWRITER + 4:
> > > + s->cwriter = deposit64(s->cwriter, 32, 32, value);
> > > + break;
> > > + case GITS_CREADR:
> > > + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
> > > + s->creadr = deposit64(s->creadr, 0, 32,
> > > + (value &
> > > ~R_GITS_CREADR_STALLED_MASK));
> > > + } else {
> > > + /* RO register, ignore the write */
> > > + qemu_log_mask(LOG_GUEST_ERROR,
> > > + "%s: invalid guest write to RO
> > > register at offset "
> > > + TARGET_FMT_plx "\n", __func__,
> > > offset);
> > > + }
> > > + break;
> > > + case GITS_CREADR + 4:
> > > + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
> > > + s->creadr = deposit64(s->creadr, 32, 32, value);
> > > + } else {
> > > + /* RO register, ignore the write */
> > > + qemu_log_mask(LOG_GUEST_ERROR,
> > > + "%s: invalid guest write to RO
> > > register at offset "
> > > + TARGET_FMT_plx "\n", __func__,
> > > offset);
> > > + }
> > > + break;
> > > + case GITS_BASER ... GITS_BASER + 0x3f:
> > > + /*
> > > + * IMPDEF choice:- GITS_BASERn register becomes RO if
> > > ITS is
> > > + * already enabled
> > > + */
> > > + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> > > + index = (offset - GITS_BASER) / 8;
> > > +
> > > + if (offset & 7) {
> > > + value <<= 32;
> > > + value &= ~GITS_BASER_RO_MASK;
> > > + s->baser[index] &= GITS_BASER_RO_MASK |
> > > MAKE_64BIT_MASK(0, 32);
> > > + s->baser[index] |= value;
> > > + } else {
> > > + value &= ~GITS_BASER_RO_MASK;
> > > + s->baser[index] &= GITS_BASER_RO_MASK |
> > > MAKE_64BIT_MASK(32, 32);
> > > + s->baser[index] |= value;
> > > + }
> > > + }
> > > + break;
> > > + case GITS_IIDR:
> > > + case GITS_IDREGS ... GITS_IDREGS + 0x2f:
> > > + /* RO registers, ignore the write */
> > > + qemu_log_mask(LOG_GUEST_ERROR,
> > > + "%s: invalid guest write to RO register at
> > > offset "
> > > + TARGET_FMT_plx "\n", __func__, offset);
> > > + break;
> > > + default:
> > > + result = MEMTX_ERROR;
> > > + break;
> > > + }
> > > return result;
> > > }
> > >
> > > @@ -49,7 +295,55 @@ static MemTxResult its_readl(GICv3ITSState
> > > *s, hwaddr offset,
> > > uint64_t *data, MemTxAttrs attrs)
> > > {
> > > MemTxResult result = MEMTX_OK;
> > > + int index;
> > >
> > > + switch (offset) {
> > > + case GITS_CTLR:
> > > + *data = s->ctlr;
> > > + break;
> > > + case GITS_IIDR:
> > > + *data = gicv3_iidr();
> > > + break;
> > > + case GITS_IDREGS ... GITS_IDREGS + 0x2f:
> > > + /* ID registers */
> > > + *data = gicv3_idreg(offset - GITS_IDREGS);
> > > + break;
> > > + case GITS_TYPER:
> > > + *data = extract64(s->typer, 0, 32);
> > > + break;
> > > + case GITS_TYPER + 4:
> > > + *data = extract64(s->typer, 32, 32);
> > > + break;
> > > + case GITS_CBASER:
> > > + *data = extract64(s->cbaser, 0, 32);
> > > + break;
> > > + case GITS_CBASER + 4:
> > > + *data = extract64(s->cbaser, 32, 32);
> > > + break;
> > > + case GITS_CREADR:
> > > + *data = extract64(s->creadr, 0, 32);
> > > + break;
> > > + case GITS_CREADR + 4:
> > > + *data = extract64(s->creadr, 32, 32);
> > > + break;
> > > + case GITS_CWRITER:
> > > + *data = extract64(s->cwriter, 0, 32);
> > > + break;
> > > + case GITS_CWRITER + 4:
> > > + *data = extract64(s->cwriter, 32, 32);
> > > + break;
> > > + case GITS_BASER ... GITS_BASER + 0x3f:
> > > + index = (offset - GITS_BASER) / 8;
> > > + if (offset & 7) {
> > > + *data = extract64(s->baser[index], 32, 32);
> > > + } else {
> > > + *data = extract64(s->baser[index], 0, 32);
> > > + }
> > > + break;
> > > + default:
> > > + result = MEMTX_ERROR;
> > > + break;
> > > + }
> > > return result;
> > > }
> > >
> > > @@ -57,7 +351,54 @@ static MemTxResult its_writell(GICv3ITSState
> > > *s, hwaddr offset,
> > > uint64_t value, MemTxAttrs attrs)
> > > {
> > > MemTxResult result = MEMTX_OK;
> > > + int index;
> > >
> > > + switch (offset) {
> > > + case GITS_BASER ... GITS_BASER + 0x3f:
> > > + /*
> > > + * IMPDEF choice:- GITS_BASERn register becomes RO if
> > > ITS is
> > > + * already enabled
> > > + */
> > > + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> > > + index = (offset - GITS_BASER) / 8;
> > > + s->baser[index] &= GITS_BASER_RO_MASK;
> > > + s->baser[index] |= (value & ~GITS_BASER_RO_MASK);
> > > + }
> > > + break;
> > > + case GITS_CBASER:
> > > + /*
> > > + * IMPDEF choice:- GITS_CBASER register becomes RO if
> > > ITS is
> > > + * already enabled
> > > + */
> > > + if (!(s->ctlr & ITS_CTLR_ENABLED)) {
> > > + s->cbaser = value;
> > > + s->creadr = 0;
> > > + s->cwriter = s->creadr;
> > > + }
> > > + break;
> > > + case GITS_CWRITER:
> > > + s->cwriter = value & ~R_GITS_CWRITER_RETRY_MASK;
> > > + break;
> > > + case GITS_CREADR:
> > > + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
> > > + s->creadr = value & ~R_GITS_CREADR_STALLED_MASK;
> > > + } else {
> > > + /* RO register, ignore the write */
> > > + qemu_log_mask(LOG_GUEST_ERROR,
> > > + "%s: invalid guest write to RO
> > > register at offset "
> > > + TARGET_FMT_plx "\n", __func__,
> > > offset);
> > > + }
> > > + break;
> > > + case GITS_TYPER:
> > > + /* RO registers, ignore the write */
> > > + qemu_log_mask(LOG_GUEST_ERROR,
> > > + "%s: invalid guest write to RO register at
> > > offset "
> > > + TARGET_FMT_plx "\n", __func__, offset);
> > > + break;
> > > + default:
> > > + result = MEMTX_ERROR;
> > > + break;
> > > + }
> > > return result;
> > > }
> > >
> > > @@ -65,7 +406,29 @@ static MemTxResult its_readll(GICv3ITSState
> > > *s, hwaddr offset,
> > > uint64_t *data, MemTxAttrs attrs)
> > > {
> > > MemTxResult result = MEMTX_OK;
> > > + int index;
> > >
> > > + switch (offset) {
> > > + case GITS_TYPER:
> > > + *data = s->typer;
> > > + break;
> > > + case GITS_BASER ... GITS_BASER + 0x3f:
> > > + index = (offset - GITS_BASER) / 8;
> > > + *data = s->baser[index];
> > > + break;
> > > + case GITS_CBASER:
> > > + *data = s->cbaser;
> > > + break;
> > > + case GITS_CREADR:
> > > + *data = s->creadr;
> > > + break;
> > > + case GITS_CWRITER:
> > > + *data = s->cwriter;
> > > + break;
> > > + default:
> > > + result = MEMTX_ERROR;
> > > + break;
> > > + }
> > > return result;
> > > }
> > >
> > > @@ -162,6 +525,9 @@ static void gicv3_arm_its_realize(DeviceState
> > > *dev, Error **errp)
> > > gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > > &gicv3_its_translation_ops);
> > >
> > > if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> > > + address_space_init(&s->gicv3->dma_as, s->gicv3->dma,
> > > + "gicv3-its-sysmem");
> > > +
> > > /* set the ITS default features supported */
> > > s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
> > > GITS_TYPE_PHYSICAL);
> > > @@ -208,6 +574,14 @@ static void gicv3_its_reset(DeviceState
> > > *dev)
> > > }
> > > }
> > >
> > > +static void gicv3_its_post_load(GICv3ITSState *s)
> > > +{
> > > + if (s->ctlr & ITS_CTLR_ENABLED) {
> > > + extract_table_params(s);
> > > + extract_cmdq_params(s);
> > > + }
> > > +}
> > > +
> > > static Property gicv3_its_props[] = {
> > > DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-
> > > gicv3",
> > > GICv3State *),
> > > @@ -218,10 +592,12 @@ static void
> > > gicv3_its_class_init(ObjectClass *klass, void *data)
> > > {
> > > DeviceClass *dc = DEVICE_CLASS(klass);
> > > GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
> > > + GICv3ITSCommonClass *icc =
> > > ARM_GICV3_ITS_COMMON_CLASS(klass);
> > >
> > > dc->realize = gicv3_arm_its_realize;
> > > device_class_set_props(dc, gicv3_its_props);
> > > device_class_set_parent_reset(dc, gicv3_its_reset, &ic-
> > > >parent_reset);
> > > + icc->post_load = gicv3_its_post_load;
> > > }
> > >
> > > static const TypeInfo gicv3_its_info = {
> > > diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
> > > index e0b06930a7..dc2c1bc45b 100644
> > > --- a/hw/intc/gicv3_internal.h
> > > +++ b/hw/intc/gicv3_internal.h
> > > @@ -238,7 +238,7 @@ FIELD(GITS_BASER, PAGESIZE, 8, 2)
> > > FIELD(GITS_BASER, SHAREABILITY, 10, 2)
> > > FIELD(GITS_BASER, PHYADDR, 12, 36)
> > > FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
> > > -FIELD(GITS_BASER, PHYADDRH_64K, 48, 4)
> > > +FIELD(GITS_BASER, PHYADDRH_64K, 12, 4)
> > should have been addressed earlier
> > > FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
> > > FIELD(GITS_BASER, OUTERCACHE, 53, 3)
> > > FIELD(GITS_BASER, TYPE, 56, 3)
> > > @@ -246,6 +246,20 @@ FIELD(GITS_BASER, INNERCACHE, 59, 3)
> > > FIELD(GITS_BASER, INDIRECT, 62, 1)
> > > FIELD(GITS_BASER, VALID, 63, 1)
> > >
> > > +FIELD(GITS_CBASER, SIZE, 0, 8)
> > > +FIELD(GITS_CBASER, SHAREABILITY, 10, 2)
> > > +FIELD(GITS_CBASER, PHYADDR, 12, 40)
> > > +FIELD(GITS_CBASER, OUTERCACHE, 53, 3)
> > > +FIELD(GITS_CBASER, INNERCACHE, 59, 3)
> > > +FIELD(GITS_CBASER, VALID, 63, 1)
> > > +
> > > +FIELD(GITS_CREADR, STALLED, 0, 1)
> > > +FIELD(GITS_CREADR, OFFSET, 5, 15)
> > > +
> > > +FIELD(GITS_CWRITER, RETRY, 0, 1)
> > > +FIELD(GITS_CWRITER, OFFSET, 5, 15)
> > > +
> > > +FIELD(GITS_CTLR, ENABLED, 0, 1)
> > > FIELD(GITS_CTLR, QUIESCENT, 31, 1)
> > >
> > > FIELD(GITS_TYPER, PHYSICAL, 0, 1)
> > > @@ -257,6 +271,13 @@ FIELD(GITS_TYPER, PTA, 19, 1)
> > > FIELD(GITS_TYPER, CIDBITS, 32, 4)
> > > FIELD(GITS_TYPER, CIL, 36, 1)
> > >
> > > +#define GITS_IDREGS 0xFFD0
> > > +
> > > +#define ITS_CTLR_ENABLED (1U) /* ITS Enabled */
> > > +
> > > +#define
> > > GITS_BASER_RO_MASK (R_GITS_BASER_ENTRYSIZE_MASK
> > > | \
> > > + R_GITS_BASER_TYPE_
> > > MASK)
> > > +
> > > #define GITS_BASER_PAGESIZE_4K 0
> > > #define GITS_BASER_PAGESIZE_16K 1
> > > #define GITS_BASER_PAGESIZE_64K 2
> > > @@ -264,6 +285,14 @@ FIELD(GITS_TYPER, CIL, 36, 1)
> > > #define GITS_ITT_TYPE_DEVICE 1ULL
> > > #define GITS_ITT_TYPE_COLLECTION 4ULL
> > >
> > > +#define GITS_PAGE_SIZE_4K 0x1000
> > > +#define GITS_PAGE_SIZE_16K 0x4000
> > > +#define GITS_PAGE_SIZE_64K 0x10000
> > > +
> > > +#define L1TABLE_ENTRY_SIZE 8
> > > +
> > > +#define GITS_CMDQ_ENTRY_SIZE 32
> > > +
> > > /**
> > > * Default features advertised by this version of ITS
> > > */
> > > diff --git a/include/hw/intc/arm_gicv3_common.h
> > > b/include/hw/intc/arm_gicv3_common.h
> > > index 91491a2f66..1fd5cedbbd 100644
> > > --- a/include/hw/intc/arm_gicv3_common.h
> > > +++ b/include/hw/intc/arm_gicv3_common.h
> > > @@ -226,6 +226,9 @@ struct GICv3State {
> > > int dev_fd; /* kvm device fd if backed by kvm vgic support
> > > */
> > > Error *migration_blocker;
> > >
> > > + MemoryRegion *dma;
> > > + AddressSpace dma_as;
> > > +
> > > /* Distributor */
> > >
> > > /* for a GIC with the security extensions the NS banked
> > > version of this
> > > diff --git a/include/hw/intc/arm_gicv3_its_common.h
> > > b/include/hw/intc/arm_gicv3_its_common.h
> > > index 65d1191db1..4e79145dde 100644
> > > --- a/include/hw/intc/arm_gicv3_its_common.h
> > > +++ b/include/hw/intc/arm_gicv3_its_common.h
> > > @@ -41,6 +41,25 @@
> > >
> > > #define GITS_TRANSLATER 0x0040
> > >
> > > +typedef struct {
> > > + bool valid;
> > > + bool indirect;
> > > + uint16_t entry_sz;
> > > + uint32_t page_sz;
> > > + uint32_t max_entries;
> > > + union {
> > > + uint32_t max_devids;
> > > + uint32_t max_collids;
> > > + } maxids;
> > > + uint64_t base_addr;
> > > +} TableDesc;
> > > +
> > > +typedef struct {
> > > + bool valid;
> > > + uint32_t max_entries;
> > > + uint64_t base_addr;
> > > +} CmdQDesc;
> > > +
> > > struct GICv3ITSState {
> > > SysBusDevice parent_obj;
> > >
> > > @@ -63,6 +82,10 @@ struct GICv3ITSState {
> > > uint64_t creadr;
> > > uint64_t baser[8];
> > >
> > > + TableDesc dt;
> > > + TableDesc ct;
> > > + CmdQDesc cq;
> > > +
> > > Error *migration_blocker;
> > > };
> > >
> > >
> > Besides
> > Reviewed-by: Eric Auger <eric.auger@redhat.com>
> >
> > Eric
> >
> >
^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2021-08-05 21:15 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework Shashi Mallela
2021-07-05 14:58 ` Peter Maydell
2021-07-05 15:55 ` shashi.mallela
2021-07-05 16:25 ` Peter Maydell
2021-07-05 17:04 ` shashi.mallela
2021-07-05 18:58 ` Peter Maydell
2021-07-07 2:08 ` shashi.mallela
2021-07-06 7:44 ` Eric Auger
2021-07-07 2:06 ` shashi.mallela
2021-06-30 15:31 ` [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added Shashi Mallela
2021-07-06 9:29 ` Eric Auger
2021-07-08 17:27 ` Eric Auger
2021-08-05 21:14 ` shashi.mallela
2021-06-30 15:31 ` [PATCH v5 03/10] hw/intc: GICv3 ITS command queue framework Shashi Mallela
2021-07-06 9:31 ` Eric Auger
2021-06-30 15:31 ` [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing Shashi Mallela
2021-07-05 14:07 ` Peter Maydell
2021-07-06 9:27 ` Eric Auger
2021-07-07 2:02 ` shashi.mallela
2021-07-05 14:54 ` Peter Maydell
2021-07-06 0:47 ` shashi.mallela
2021-07-06 3:25 ` shashi.mallela
2021-07-06 9:19 ` Peter Maydell
2021-07-06 12:46 ` shashi.mallela
2021-07-06 13:27 ` Peter Maydell
2021-07-07 2:08 ` shashi.mallela
2021-07-06 10:04 ` Eric Auger
2021-07-06 10:07 ` Peter Maydell
2021-07-06 10:05 ` Eric Auger
2021-06-30 15:31 ` [PATCH v5 05/10] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
2021-07-05 14:20 ` Peter Maydell
2021-06-30 15:31 ` [PATCH v5 06/10] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
2021-07-05 14:43 ` Peter Maydell
2021-06-30 15:31 ` [PATCH v5 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela
2021-07-05 14:59 ` Peter Maydell
2021-06-30 15:31 ` [PATCH v5 08/10] tests/data/acpi/virt: Add IORT files for ITS Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 09/10] hw/arm/virt: add ITS support in virt GIC Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 10/10] tests/data/acpi/virt: Update IORT files for ITS Shashi Mallela
2021-07-05 15:02 ` Peter Maydell
2021-07-05 15:05 ` [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Peter Maydell
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