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[142.114.143.47]) by smtp.gmail.com with ESMTPSA id t7sm4118909qkm.23.2021.07.05.20.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 20:25:39 -0700 (PDT) Message-ID: <287eb50c0b99a3daec986ec29ede33cb2bdfd025.camel@linaro.org> Subject: Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing From: shashi.mallela@linaro.org To: Peter Maydell Date: Mon, 05 Jul 2021 23:25:38 -0400 In-Reply-To: References: <20210630153156.9421-1-shashi.mallela@linaro.org> <20210630153156.9421-5-shashi.mallela@linaro.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-16.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::72f; envelope-from=shashi.mallela@linaro.org; helo=mail-qk1-x72f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , Radoslaw Biernacki , QEMU Developers , qemu-arm , Igor Mammedov , Leif Lindholm Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, 2021-07-05 at 20:47 -0400, shashi.mallela@linaro.org wrote: > On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote: > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela < > > shashi.mallela@linaro.org> wrote: > > > Added ITS command queue handling for MAPTI,MAPI commands,handled > > > ITS > > > translation which triggers an LPI via INT command as well as > > > write > > > to GITS_TRANSLATER register,defined enum to differentiate between > > > ITS > > > command interrupt trigger and GITS_TRANSLATER based interrupt > > > trigger. > > > Each of these commands make use of other functionalities > > > implemented to > > > get device table entry,collection table entry or interrupt > > > translation > > > table entry required for their processing. > > > > > > Signed-off-by: Shashi Mallela > > > --- > > > +static MemTxResult process_mapti(GICv3ITSState *s, uint64_t > > > value, > > > + uint32_t offset, bool > > > ignore_pInt) > > > +{ > > > + AddressSpace *as = &s->gicv3->dma_as; > > > + uint32_t devid, eventid; > > > + uint32_t pIntid = 0; > > > + uint32_t max_eventid, max_Intid; > > > + bool dte_valid; > > > + MemTxResult res = MEMTX_OK; > > > + uint16_t icid = 0; > > > + uint64_t dte = 0; > > > + IteEntry ite; > > > + uint32_t int_spurious = INTID_SPURIOUS; > > > + uint64_t idbits; > > > + > > > + devid = ((value & DEVID_MASK) >> DEVID_SHIFT); > > > + offset += NUM_BYTES_IN_DW; > > > + value = address_space_ldq_le(as, s->cq.base_addr + offset, > > > + MEMTXATTRS_UNSPECIFIED, &res); > > > + > > > + if (res != MEMTX_OK) { > > > + return res; > > > + } > > > + > > > + eventid = (value & EVENTID_MASK); > > > + > > > + if (!ignore_pInt) { > > > + pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT); > > > + } > > > + > > > + offset += NUM_BYTES_IN_DW; > > > + value = address_space_ldq_le(as, s->cq.base_addr + offset, > > > + MEMTXATTRS_UNSPECIFIED, &res); > > > + > > > + if (res != MEMTX_OK) { > > > + return res; > > > + } > > > + > > > + icid = value & ICID_MASK; > > > + > > > + dte = get_dte(s, devid, &res); > > > + > > > + if (res != MEMTX_OK) { > > > + return res; > > > + } > > > + dte_valid = dte & TABLE_ENTRY_VALID_MASK; > > > + > > > + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1)); > > > + > > > + if (!ignore_pInt) { > > > + idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser, > > > GICR_PROPBASER, > > > + IDBITS), GICD_TYPER_IDBITS); > > > > I missed this the first time around, but I don't think this is > > right. > > Different CPUs could have different GICR_PROPBASER values, so > > checking > > against just one of them is wrong. The pseudocode only tests > > LPIOutOfRange() > > which is documented as testing "larger than GICD_TYPER.IDbits or > > not > > in > > the LPI range and not 1023". So I don't think we should be looking > > at the GICR_PROPBASER field here. > > > > More generally, "s->gicv3->cpu->something" is usually going to be > > wrong, because it is implicitly looking at CPU 0; often either > > there > > should be something else telling is which CPU to use (as in > > &s->gicv3->cpu[rdbase] where the CTE told us which redistributor), > > or we might need to operate on all CPUs/redistributors. The only > > exception is where we can guarantee that all the CPUs are the same > > (eg when looking at GICR_TYPER.PLPIS.) > In that case,the validation of IDBITS(in case of ITS enabled) could > be > done during the write of gicr_propbaser register value itself(in > arm_gicv3_redist.c) and the its command processing code here can just > extract the idbits for its use. > > thanks > > -- PMM Hi Peter Please ignore my last comment. To address this scenario,i think the feasible option would be to call get_cte() to get the rdbase corresponding to icid value passed to mapti command.Since each icid is mapped to a rdbase(by virtue of calling MAPC command),if the collection table has a valid mapping for this icid we continue processing this MAPTI command using &s->gicv3->cpu[rdbase] applicable propbaser value to validate idbits, else return without further processing. Thanks Shashi