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From: "Cédric Le Goater" <clg@kaod.org>
To: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>,
	linux-mtd@lists.infradead.org
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>,
	Robert Lippert <rlippert@google.com>,
	Richard Weinberger <richard@nod.at>,
	Marek Vasut <marek.vasut@gmail.com>,
	Robert Lippert <roblip@gmail.com>,
	Brian Norris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH 2/4] mtd: spi-nor: aspeed: add support for SPI dual IO read mode
Date: Wed, 21 Jun 2017 14:25:45 +0200	[thread overview]
Message-ID: <28db8eb7-7680-84fe-4352-7d69332de375@kaod.org> (raw)
In-Reply-To: <c529137d-f52e-48b2-caa3-670d62d7163d@kaod.org>

On 06/21/2017 09:32 AM, Cédric Le Goater wrote:
> On 06/21/2017 12:50 AM, Cyrille Pitchen wrote:
>> Hi Cédric,
>>
>>
>> Le 20/04/2017 à 13:56, Cédric Le Goater a écrit :
>>> From: Robert Lippert <roblip@gmail.com>
>>>
>>> Implements support for the dual IO read mode on aspeed SMC/FMC
>>> controllers which uses both MISO and MOSI lines for data during a read
>>> to double the read bandwidth.
>>>
>>> Signed-off-by: Robert Lippert <rlippert@google.com>
>>> [clg: adapted to mainline driver ]
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>>  drivers/mtd/spi-nor/aspeed-smc.c | 19 ++++++++++++++-----
>>>  1 file changed, 14 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
>>> index 2940f2098420..183d950e621b 100644
>>> --- a/drivers/mtd/spi-nor/aspeed-smc.c
>>> +++ b/drivers/mtd/spi-nor/aspeed-smc.c
>>> @@ -372,12 +372,20 @@ static ssize_t aspeed_smc_read_user(struct spi_nor *nor, loff_t from,
>>>  	struct aspeed_smc_chip *chip = nor->priv;
>>>  	int i;
>>>  	u8 dummy = 0xFF;
>>> +	u32 ctl;
>>>  
>>>  	aspeed_smc_start_user(nor);
>>>  	aspeed_smc_send_cmd_addr(nor, nor->read_opcode, from);
>>>  	for (i = 0; i < chip->nor.read_dummy / 8; i++)
>>>  		aspeed_smc_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
>>>  
>>> +	if (chip->nor.flash_read == SPI_NOR_DUAL) {
>>> +		/* Switch to dual I/O mode for data cycle */
>>> +		ctl = readl(chip->ctl) & ~CONTROL_IO_MODE_MASK;
>>> +		ctl |= CONTROL_IO_DUAL_DATA;
>>> +		writel(ctl, chip->ctl);
>>> +	}
>>> +
>>
>> As expected this patch doesn't apply as is to the spi-nor/next branch of
>> l2-mtd because flash_read and SPI_NOR_{DUAL|QUAD} enums no longer exists.
>>
>> Besides it looks like the Aspeed controller can support SPI 1-2-2 as
>> well as SPI 1-1-2.
>>
>> I see:
>> #define CONTROL_IO_DUAL_DATA		BIT(29)
>> #define CONTROL_IO_DUAL_ADDR_DATA	(BIT(29) | BIT(28))
>>
>> Now spi_nor_scan() makes the difference between these 2 SPI protocols.
>>
>> Besides, you may also want to use the compatible DT string to make the
>> difference between Aspeed controllers also supporting SPI 1-1-4 and SPI
>> 1-4-4 and other controllers supporting only Dual SPI protocols so you
>> could fill the hwcaps parameter of spi_nor_scan() as needed.
>>
>> So I think we should spend a little more time to rework this patch.
> 
> OK. I will take a look.
> 
> Please consider taking :
> 
>   [PATCH 4/4] mtd: spi-nor: aspeed: use command mode for reads

Forget it. I am having issues with this patch on newer kernels. I will 
cook a patchset after the merge window.

Thanks,

C. 
   
 
> while I reconcile my patchset with the spi-nor tree.
> 
> Thanks,
> 
> C.
> 
>>
>>>  	aspeed_smc_read_from_ahb(read_buf, chip->ahb_base, len);
>>>  	aspeed_smc_stop_user(nor);
>>>  	return len;
>>> @@ -591,6 +599,9 @@ static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip)
>>>  	case SPI_NOR_FAST:
>>>  		cmd = CONTROL_COMMAND_MODE_FREAD;
>>>  		break;
>>> +	case SPI_NOR_DUAL:
>>> +		cmd = CONTROL_COMMAND_MODE_FREAD | CONTROL_IO_DUAL_DATA;
>>> +		break;
>>>  	default:
>>>  		dev_err(chip->nor.dev, "unsupported SPI read mode\n");
>>>  		return -EINVAL;
>>> @@ -599,7 +610,7 @@ static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip)
>>>  	chip->ctl_val[smc_read] |= cmd |
>>>  		CONTROL_IO_DUMMY_SET(chip->nor.read_dummy / 8);
>>>  
>>> -	dev_dbg(controller->dev, "base control register: %08x\n",
>>> +	dev_dbg(controller->dev, "read control register: %08x\n",
>>>  		chip->ctl_val[smc_read]);
>>>  	return 0;
>>>  }
>>> @@ -670,11 +681,9 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
>>>  			break;
>>>  
>>>  		/*
>>> -		 * TODO: Add support for SPI_NOR_QUAD and SPI_NOR_DUAL
>>> -		 * attach when board support is present as determined
>>> -		 * by of property.
>>> +		 * Aspeed SoCs only support Dual mode
>>>  		 */
>>> -		ret = spi_nor_scan(nor, NULL, SPI_NOR_NORMAL);
>>> +		ret = spi_nor_scan(nor, NULL, SPI_NOR_DUAL);
>>>  		if (ret)
>>>  			break;
>>>  
>>>
>>
> 

  reply	other threads:[~2017-06-21 12:26 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-20 11:56 [PATCH 0/4] mtd: spi-nor: aspeed: add dual read and command mode support Cédric Le Goater
2017-04-20 11:56 ` [PATCH 1/4] mtd: spi-nor: aspeed: remove dummies from keep mask Cédric Le Goater
2017-04-20 13:28   ` Marek Vasut
2017-06-20 22:25     ` Cyrille Pitchen
2017-04-20 11:56 ` [PATCH 2/4] mtd: spi-nor: aspeed: add support for SPI dual IO read mode Cédric Le Goater
2017-04-20 13:28   ` Marek Vasut
2017-06-20 22:50   ` Cyrille Pitchen
2017-06-21  7:32     ` Cédric Le Goater
2017-06-21 12:25       ` Cédric Le Goater [this message]
2017-06-21 22:46         ` Cyrille Pitchen
2017-04-20 11:56 ` [PATCH 3/4] mtd: spi-nor: aspeed: configure chip window on AHB bus Cédric Le Goater
2017-04-20 13:30   ` Marek Vasut
2017-06-20 22:34     ` Cyrille Pitchen
2017-04-20 11:56 ` [PATCH 4/4] mtd: spi-nor: aspeed: use command mode for reads Cédric Le Goater
2017-04-20 13:31   ` Marek Vasut
2017-04-20 13:33     ` Richard Weinberger
2017-04-20 13:53     ` Cédric Le Goater
2017-04-20 13:58       ` Marek Vasut
2017-06-20  7:10         ` Cédric Le Goater
2017-06-20  9:07         ` Cédric Le Goater
     [not found]           ` <2bd0b105-7652-8917-4a1d-6f218eaf848e@atmel.com>
2017-06-20 13:49             ` Cédric Le Goater
2017-06-20 14:06             ` Cédric Le Goater
2018-06-22 12:14 [PATCH 0/4] mtd: spi-nor: aspeed: introduce optimized settings for fast reads Cédric Le Goater
2018-06-22 12:14 ` [PATCH 2/4] mtd: spi-nor: aspeed: add support for SPI dual IO read mode Cédric Le Goater
2018-07-23 12:12   ` Joel Stanley

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