From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753430AbbL2Nwx (ORCPT ); Tue, 29 Dec 2015 08:52:53 -0500 Received: from mout.kundenserver.de ([212.227.126.187]:55065 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751964AbbL2Nwv (ORCPT ); Tue, 29 Dec 2015 08:52:51 -0500 From: Arnd Bergmann To: Rongrong Zou Cc: catalin.marinas@arm.com, will.deacon@arm.com, benh@kernel.crashing.org, lijianhua@huawei.com, lixiancai@huawei.com, linuxarm@huawei.com, linux-kernel@vger.kernel.org, minyard@acm.org, gregkh@linuxfoundation.org Subject: Re: [PATCH v1 3/3] ARM64 LPC: update binding doc Date: Tue, 29 Dec 2015 14:52:32 +0100 Message-ID: <2936049.MPnkGvH5pC@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <1451396032-23708-4-git-send-email-zourongrong@gmail.com> References: <1451396032-23708-1-git-send-email-zourongrong@gmail.com> <1451396032-23708-4-git-send-email-zourongrong@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:6gcwCPwxLZR2B4FZ+Hozzxo8qgHStt5YpYy6UQm4ob1JvQeb1a3 9DO+bc//p2+a/oJoKw+LIBQ/A2u054qkse1wPVxU1BofGG3cHC5jPWtp9WM1uQ7oPuoXfjo Ye6wv+XobZgYiqHHHDADxuGg0mIzoZshmPN7YDZJiXZ11uEcLWCePzuLEnq4JL/+5mfNWjc 4jCm1cguiLFWgkiR07qPQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:UboEgAC3noU=:shwOde1pyjcerr2SPZlQhA 21/kLQ+uv8+5meX91bK/SWsbRKpeR438WDouSKIx4LvsP2mURXhNbVS4lB2IUHMOJ3Dbo4kNn h15M9TO3inV47U16WfUHGEZWPB7Ck8WfXGCGGVjVZoUsEhA8kSiSn0cmUg5DJqg+3AbVfMHuM M+dUuY6Gtyt/smnPIkcWNPrUn7S2C/k2aszCbxtYUWugndMdeDwAbBxrzfQtealHZrXQ/8E15 rd+B6sMGGYrcrMwLmwacYPXDLvpfUop+Jufs1j2RhA0yqRnHCmstqmXDVbN9RZjEaMoLjYYVM sPYyKeIYxRxIkLxhztLKXn6UpXV+K5eFp1ppBXF/lOD66MDOSuClsfOHxctxpaOL4OSRb3JBS 4ZK7bALQBsB9/xyO7sreOHlYkVIKKozfwhm2rrVLCg9WjW1l/o9R74Cj9xASD0rxDc82kB4Cs xI3uC+vKKFIHgBrx4hEZFa/kod+sMSs+4dvJ/UcaSeg7Q6062e4yvOAbbBWtoImF/vgqV1xlz +kRGfC2dCtQtqdJfWfaYdpmq3g3/2/yJLsZCWP+kw4Y+ZlL+yHCHFfCY/fmHblhyB2iLBXZcD 22f+2xVNoytVuvCSZIpla25L2ykAxt8crBHkPhVx10sNMDAdoeYgRXHe9MvgVdcCroh9vgA2V tcJ+Xrc6jYxrdq4Z9FL6K0cN4dBgzkjDQ+Mzkflr2N+FFq6PdlCQIY4nQSpumUiHLG39qDElm 0rnviA7KFpjNIMkx Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 29 December 2015 21:33:52 Rongrong Zou wrote: > Signed-off-by: Rongrong Zou > --- > .../devicetree/bindings/arm64/low-pin-count.txt | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm64/low-pin-count.txt Please add a patch description above and Cc the devicetree mailing list when you submit it again. > diff --git a/Documentation/devicetree/bindings/arm64/low-pin-count.txt b/Documentation/devicetree/bindings/arm64/low-pin-count.txt > new file mode 100644 > index 0000000..215f2c4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm64/low-pin-count.txt > @@ -0,0 +1,20 @@ > +Low Pin Count bus driver > + > +Usually LPC controller is part of PCI host bridge, so the legacy ISA > +port locate on LPC bus can be accessed directly. But some SoC have > +independent LPC controller, and we can access the legacy port by specifying > +LPC address cycle. Thus, LPC driver is introduced. > + > +Required properties: > +- compatible: "low-pin-count" > +- reg: specifies low pin count address range > + It would be good to add an explanation about the address space for child devices. Arnd