From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752881AbbDUHRc (ORCPT ); Tue, 21 Apr 2015 03:17:32 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:58056 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750747AbbDUHRa (ORCPT ); Tue, 21 Apr 2015 03:17:30 -0400 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: Feng Kan , Marc Zyngier , linux-pci@vger.kernel.org, Duc Dang , Liviu Dudau , "linux-kernel@vger.kernel.org" , Bjorn Helgaas , Tanmay Inamdar , Grant Likely , Loc Ho Subject: Re: [PATCH v4 1/4] PCI: X-Gene: Add the APM X-Gene v1 PCIe MSI/MSIX termination driver Date: Tue, 21 Apr 2015 09:16:49 +0200 Message-ID: <2940382.sQOGMMprLX@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: References: <3188893.aaXgNln69B@wuerfel> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:iPeojQajlLMTqfHxGu3kLxSCKotLDsYkxHnIyJMrsI6a4Rm27xz CnSo3yr9IZu9qK2vMOffxoohDeb1Kub7soSokEysQHLgNlc8PuSRmBgmgM+5XT/UXFMfD8m BQkk5iuRWPUAE+T8fAmveBv9Cxp7f7H79xqEhFsHX7EAX13b5igdDOs1d/dHRIyA3Eo1xFL 13576CmN/j09eHycllQUQ== X-UI-Out-Filterresults: notjunk:1; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday 20 April 2015 11:49:37 Feng Kan wrote: > > > > Obviously they appear on the PCI host bridge in order, because that > > is a how PCI works. My question was about what happens then. On a lot > > of SoCs, there is something like an AXI bus that uses posted > > transactions between PCI and RAM, so you have a do a full manual > > syncronization of ongoing PIC DMAs when the MSI catcher signals the > > top-level interrupt. Do you have a bus between PCI and RAM that does > > not require this, or does the MSI catcher have logic to flush all DMAs? > > Our hardware has an automatic mechanism to flush the content to DRAM before the > MSI write is committed. Ok, excellent! Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: arnd@arndb.de (Arnd Bergmann) Date: Tue, 21 Apr 2015 09:16:49 +0200 Subject: [PATCH v4 1/4] PCI: X-Gene: Add the APM X-Gene v1 PCIe MSI/MSIX termination driver In-Reply-To: References: <3188893.aaXgNln69B@wuerfel> Message-ID: <2940382.sQOGMMprLX@wuerfel> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Monday 20 April 2015 11:49:37 Feng Kan wrote: > > > > Obviously they appear on the PCI host bridge in order, because that > > is a how PCI works. My question was about what happens then. On a lot > > of SoCs, there is something like an AXI bus that uses posted > > transactions between PCI and RAM, so you have a do a full manual > > syncronization of ongoing PIC DMAs when the MSI catcher signals the > > top-level interrupt. Do you have a bus between PCI and RAM that does > > not require this, or does the MSI catcher have logic to flush all DMAs? > > Our hardware has an automatic mechanism to flush the content to DRAM before the > MSI write is committed. Ok, excellent! Arnd