Re: [PATCH v2 2/3] hw/arm/mps2: New board model mps2-an500

["Philippe Mathieu-Daudé" <f4bug@amsat.org>]

On 9/3/20 10:20 PM, Peter Maydell wrote:
> Implement a model of the MPS2 with the AN500 firmware. This is
> similar to the AN385, with the following differences:
>  * Cortex-M7 CPU
>  * PSRAM is at 0x6000_0000
>  * Ethernet is at 0xa000_0000
>  * No zbt_boot_ctrl remapping of the low 16K
>    (but QEMU doesn't implement this anyway)
>  * no "block RAM" at 0x01000000
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> The AN500 also defines some behaviour for CFG_REG[2567] in
> the SCC (QEMU hw/misc/mps2-scc.c) but none of it is anything
> QEMU can conveniently support so I have left that code as-is
> (a guest accessing those registers will hit the LOG_GUEST_ERROR
> case for "bad offset").
> 
> Tested with a buildroot image created using the instructions at:
>  https://community.arm.com/developer/tools-software/oss-platforms/w/docs/578/running-uclinux-on-the-arm-mps2-platform
> and the "arm_mps2_CM7fpga" defconfig; QEMU commandline is
>  qemu-system-arm -M mps2-an500 -serial stdio -display none -kernel boot.axf -device loader,file=linux.axf

Maybe worth adding in the commit description.

Ideally we should add an acceptance test...

> ---
>  docs/system/arm/mps2.rst |  6 ++--
>  hw/arm/mps2.c            | 71 ++++++++++++++++++++++++++++++++--------
>  2 files changed, 62 insertions(+), 15 deletions(-)
> 
> diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
> index e680a4ceb71..7f2e9c8d52e 100644
> --- a/docs/system/arm/mps2.rst
> +++ b/docs/system/arm/mps2.rst
> @@ -1,5 +1,5 @@
> -Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
> -================================================================================================
> +Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
> +================================================================================================================
>  
>  These board models all use Arm M-profile CPUs.
>  
> @@ -14,6 +14,8 @@ QEMU models the following FPGA images:
>    Cortex-M3 as documented in ARM Application Note AN385
>  ``mps2-an386``
>    Cortex-M4 as documented in ARM Application Note AN386
> +``mps2-an500``
> +  Cortex-M7 as documented in ARM Application Note AN500
>  ``mps2-an511``
>    Cortex-M3 'DesignStart' as documented in AN511
>  ``mps2-an505``
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index 559b297e788..d17fd7a7cb5 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -16,6 +16,7 @@
>   * We model the following FPGA images:
>   *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
>   *  "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
> + *  "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
>   *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
>   *
>   * Links to the TRM for the board itself and to the various Application
> @@ -49,6 +50,7 @@
>  typedef enum MPS2FPGAType {
>      FPGA_AN385,
>      FPGA_AN386,
> +    FPGA_AN500,
>      FPGA_AN511,
>  } MPS2FPGAType;
>  
> @@ -56,6 +58,9 @@ typedef struct {
>      MachineClass parent;
>      MPS2FPGAType fpga_type;
>      uint32_t scc_id;
> +    bool has_block_ram;
> +    hwaddr ethernet_base;
> +    hwaddr psram_base;
>  } MPS2MachineClass;
>  
>  typedef struct {
> @@ -82,6 +87,7 @@ typedef struct {
>  #define TYPE_MPS2_MACHINE "mps2"
>  #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
>  #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
> +#define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
>  #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
>  
>  #define MPS2_MACHINE(obj)                                       \
> @@ -143,13 +149,14 @@ static void mps2_common_init(MachineState *machine)
>       * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
>       * call the 16MB our "system memory", as it's the largest lump.
>       *
> -     * Common to both boards:
> -     *  0x21000000..0x21ffffff : PSRAM (16MB)
> +     * AN385/AN386/AN511:
> +     *  0x21000000 .. 0x21ffffff : PSRAM (16MB)

^ Actually this belong to the previous patch.

> -     * AN385/AN386 only:
> +     * AN385/AN386/AN500:
>       *  0x00000000 .. 0x003fffff : ZBT SSRAM1
>       *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
>       *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
>       *  0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
> +     * AN385/AN386 only:

Ditto?

Otherwise:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

>       *  0x01000000 .. 0x01003fff : block RAM (16K)
>       *  0x01004000 .. 0x01007fff : mirror of above
>       *  0x01008000 .. 0x0100bfff : mirror of above
> @@ -159,22 +166,17 @@ static void mps2_common_init(MachineState *machine)
>       *  0x00400000 .. 0x007fffff : ZBT SSRAM1
>       *  0x20000000 .. 0x2001ffff : SRAM
>       *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
> +     * AN500 only:
> +     *  0x60000000 .. 0x60ffffff : PSRAM (16MB)
>       *
>       * The AN385/AN386 has a feature where the lowest 16K can be mapped
>       * either to the bottom of the ZBT SSRAM1 or to the block RAM.
>       * This is of no use for QEMU so we don't implement it (as if
>       * zbt_boot_ctrl is always zero).
>       */
> -    memory_region_add_subregion(system_memory, 0x21000000, machine->ram);
> +    memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram);
>  
> -    switch (mmc->fpga_type) {
> -    case FPGA_AN385:
> -    case FPGA_AN386:
> -        make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
> -        make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
> -        make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
> -        make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
> -                       &mms->ssram23, 0x20400000);
> +    if (mmc->has_block_ram) {
>          make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
>          make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
>                         &mms->blockram, 0x01004000);
> @@ -182,6 +184,17 @@ static void mps2_common_init(MachineState *machine)
>                         &mms->blockram, 0x01008000);
>          make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
>                         &mms->blockram, 0x0100c000);
> +    }
> +
> +    switch (mmc->fpga_type) {
> +    case FPGA_AN385:
> +    case FPGA_AN386:
> +    case FPGA_AN500:
> +        make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
> +        make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
> +        make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
> +        make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
> +                       &mms->ssram23, 0x20400000);
>          break;
>      case FPGA_AN511:
>          make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
> @@ -198,6 +211,7 @@ static void mps2_common_init(MachineState *machine)
>      switch (mmc->fpga_type) {
>      case FPGA_AN385:
>      case FPGA_AN386:
> +    case FPGA_AN500:
>          qdev_prop_set_uint32(armv7m, "num-irq", 32);
>          break;
>      case FPGA_AN511:
> @@ -235,6 +249,7 @@ static void mps2_common_init(MachineState *machine)
>      switch (mmc->fpga_type) {
>      case FPGA_AN385:
>      case FPGA_AN386:
> +    case FPGA_AN500:
>      {
>          /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
>           * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
> @@ -384,7 +399,7 @@ static void mps2_common_init(MachineState *machine)
>      /* In hardware this is a LAN9220; the LAN9118 is software compatible
>       * except that it doesn't support the checksum-offload feature.
>       */
> -    lan9118_init(&nd_table[0], 0x40200000,
> +    lan9118_init(&nd_table[0], mmc->ethernet_base,
>                   qdev_get_gpio_in(armv7m,
>                                    mmc->fpga_type == FPGA_AN511 ? 47 : 13));
>  
> @@ -413,6 +428,9 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
>      mmc->fpga_type = FPGA_AN385;
>      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
>      mmc->scc_id = 0x41043850;
> +    mmc->psram_base = 0x21000000;
> +    mmc->ethernet_base = 0x40200000;
> +    mmc->has_block_ram = true;
>  }
>  
>  static void mps2_an386_class_init(ObjectClass *oc, void *data)
> @@ -424,6 +442,23 @@ static void mps2_an386_class_init(ObjectClass *oc, void *data)
>      mmc->fpga_type = FPGA_AN386;
>      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
>      mmc->scc_id = 0x41043860;
> +    mmc->psram_base = 0x21000000;
> +    mmc->ethernet_base = 0x40200000;
> +    mmc->has_block_ram = true;
> +}
> +
> +static void mps2_an500_class_init(ObjectClass *oc, void *data)
> +{
> +    MachineClass *mc = MACHINE_CLASS(oc);
> +    MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
> +
> +    mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7";
> +    mmc->fpga_type = FPGA_AN500;
> +    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7");
> +    mmc->scc_id = 0x41045000;
> +    mmc->psram_base = 0x60000000;
> +    mmc->ethernet_base = 0xa0000000;
> +    mmc->has_block_ram = false;
>  }
>  
>  static void mps2_an511_class_init(ObjectClass *oc, void *data)
> @@ -435,6 +470,9 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)
>      mmc->fpga_type = FPGA_AN511;
>      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
>      mmc->scc_id = 0x41045110;
> +    mmc->psram_base = 0x21000000;
> +    mmc->ethernet_base = 0x40200000;
> +    mmc->has_block_ram = false;
>  }
>  
>  static const TypeInfo mps2_info = {
> @@ -458,6 +496,12 @@ static const TypeInfo mps2_an386_info = {
>      .class_init = mps2_an386_class_init,
>  };
>  
> +static const TypeInfo mps2_an500_info = {
> +    .name = TYPE_MPS2_AN500_MACHINE,
> +    .parent = TYPE_MPS2_MACHINE,
> +    .class_init = mps2_an500_class_init,
> +};
> +
>  static const TypeInfo mps2_an511_info = {
>      .name = TYPE_MPS2_AN511_MACHINE,
>      .parent = TYPE_MPS2_MACHINE,
> @@ -469,6 +513,7 @@ static void mps2_machine_init(void)
>      type_register_static(&mps2_info);
>      type_register_static(&mps2_an385_info);
>      type_register_static(&mps2_an386_info);
> +    type_register_static(&mps2_an500_info);
>      type_register_static(&mps2_an511_info);
>  }
>  
>