From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D2D8C54EBD for ; Thu, 12 Jan 2023 08:34:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236522AbjALId5 (ORCPT ); Thu, 12 Jan 2023 03:33:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239547AbjALIdd (ORCPT ); Thu, 12 Jan 2023 03:33:33 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 79F4F227; Thu, 12 Jan 2023 00:33:32 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5EBA412FC; Thu, 12 Jan 2023 00:34:14 -0800 (PST) Received: from [192.168.1.12] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8CC0C3F71A; Thu, 12 Jan 2023 00:33:30 -0800 (PST) Message-ID: <29f24401-8e39-ea40-52f6-a03c428ca445@arm.com> Date: Thu, 12 Jan 2023 09:33:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 From: Pierre Gondois Subject: Re: [PATCH v2 20/23] arm64: dts: Update cache properties for socionext To: LKML Cc: Rob Herring , Krzysztof Kozlowski , Kunihiko Hayashi , Masami Hiramatsu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20221107155825.1644604-1-pierre.gondois@arm.com> <20221107155825.1644604-21-pierre.gondois@arm.com> Content-Language: en-US In-Reply-To: <20221107155825.1644604-21-pierre.gondois@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org (subset for cc list) Hello, Just a reminder in case the patch was forgotten, Regards, Pierre On 11/7/22 16:57, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > The 'cache-unified' property should be present if one of the > properties for unified cache is present ('cache-size', ...). > > Update the Device Trees accordingly. > > Signed-off-by: Pierre Gondois > --- > arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 + > arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++ > arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 + > 3 files changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > index 1c76b4375b2e..6e1e00939214 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > @@ -52,6 +52,7 @@ cpu1: cpu@1 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > index 9308458f9611..db7d20a1a301 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > @@ -86,10 +86,12 @@ cpu3: cpu@101 { > > a72_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > a53_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > index b0c29510a7da..9ce544c9ea0a 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > @@ -83,6 +83,7 @@ cpu3: cpu@3 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 776B8C54EBD for ; Thu, 12 Jan 2023 08:34:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Thu, 12 Jan 2023 08:33:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5EBA412FC; Thu, 12 Jan 2023 00:34:14 -0800 (PST) Received: from [192.168.1.12] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8CC0C3F71A; Thu, 12 Jan 2023 00:33:30 -0800 (PST) Message-ID: <29f24401-8e39-ea40-52f6-a03c428ca445@arm.com> Date: Thu, 12 Jan 2023 09:33:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 From: Pierre Gondois Subject: Re: [PATCH v2 20/23] arm64: dts: Update cache properties for socionext To: LKML Cc: Rob Herring , Krzysztof Kozlowski , Kunihiko Hayashi , Masami Hiramatsu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20221107155825.1644604-1-pierre.gondois@arm.com> <20221107155825.1644604-21-pierre.gondois@arm.com> Content-Language: en-US In-Reply-To: <20221107155825.1644604-21-pierre.gondois@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230112_003335_768425_010BA27D X-CRM114-Status: GOOD ( 14.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org (subset for cc list) Hello, Just a reminder in case the patch was forgotten, Regards, Pierre On 11/7/22 16:57, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > The 'cache-unified' property should be present if one of the > properties for unified cache is present ('cache-size', ...). > > Update the Device Trees accordingly. > > Signed-off-by: Pierre Gondois > --- > arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 + > arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++ > arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 + > 3 files changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > index 1c76b4375b2e..6e1e00939214 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > @@ -52,6 +52,7 @@ cpu1: cpu@1 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > index 9308458f9611..db7d20a1a301 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > @@ -86,10 +86,12 @@ cpu3: cpu@101 { > > a72_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > a53_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > index b0c29510a7da..9ce544c9ea0a 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > @@ -83,6 +83,7 @@ cpu3: cpu@3 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel