From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nadav Amit Subject: x86: Question regarding the reset value of LINT0 Date: Wed, 8 Apr 2015 19:40:32 +0300 Message-ID: <2B474EEE-85C9-47C3-89FF-C56754CFEC0D@gmail.com> Mime-Version: 1.0 (Mac OS X Mail 8.2 \(2070.6\)) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE To: kvm list Return-path: Received: from mail-wg0-f45.google.com ([74.125.82.45]:33046 "EHLO mail-wg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753364AbbDHQkg convert rfc822-to-8bit (ORCPT ); Wed, 8 Apr 2015 12:40:36 -0400 Received: by wgin8 with SMTP id n8so94265873wgi.0 for ; Wed, 08 Apr 2015 09:40:35 -0700 (PDT) Received: from nadav-mbp.cs.technion.ac.il ([132.68.46.112]) by mx.google.com with ESMTPSA id hj10sm16331858wjc.48.2015.04.08.09.40.33 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 Apr 2015 09:40:33 -0700 (PDT) Sender: kvm-owner@vger.kernel.org List-ID: Hi, I would appreciate if someone explains the reason for enabling LINT0 du= ring APIC reset. This does not correspond with Intel SDM Figure 10-8: =E2=80= =9CLocal Vector Table=E2=80=9D that says all LVT registers are reset to 0x10000. In kvm_lapic_reset, I see: apic_set_reg(apic, APIC_LVT0, SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); Which is actually pretty similar to QEMU=E2=80=99s apic_reset_common: if (bsp) { /* * LINT0 delivery mode on CPU #0 is set to ExtInt at initializa= tion * time typically by BIOS, so PIC interrupt can be delivered to= the * processor when local APIC is enabled. */ s->lvt[APIC_LVT_LINT0] =3D 0x700; } Yet, in both cases, I miss the point - if it is typically done by the B= IOS, why does QEMU or KVM enable it? BTW: KVM seems to run fine without it, and I think setting it causes me problems in certain cases. Thanks, Nadav