[U-Boot] Possible Denx m28evk ethernet problem + solution

["Robert Deliën" <robert@delien.nl>]

>> I'm currently working on U-Boot support for the Freescale i.mx28evk board.
> 
> This is already supported mainline.

Hm; my workspace is quite up-to-date, but I didn't find it. What configuration
should I use for the Freescale i.mx28evk board? m28evk_config boots the
board, but not much more. The difference between the Freescale i.mx28evk
board and the Denx m28evk modules are too big (eg. ssp2 for mmc1, etc.)

> The DENX board is actually ok, working properly,

I don't doubt the working of the Denx module; I'm sure it works fine, but I don't
have one laying around, so I cannot check. However, the configuration for the
Denx m28evk module doesn't work very well on the Freescale i.mx28evk board.

> you don't understand what's 
> going on in there.

No need to be harsh; I don't have a diagram of the Denx board, so I don't
know what clock configuration was chosen for it's design.

> The RMII mode of PHY supplies clock to CPU. Read the manual 
> before you start doing some wild acusations please :-)

On my board, there wasn't any clock signal between the SoC and the PHYs,
regardless of who's supposed to source it. I can lift R171 and check who's
supplying it after my modification, but I'm pretty sure it's the SoC. This situation
works, but may still be wrong; No argument there. But this is the same
situation as the old Freescale supplied u-boot 2009.08 does it.

I don't see how the LAN8720 PHY can supply a clock to the SoC. XTAL1 is
an output only and XTAL2 is only intended to drive a chrystal, and not
connected anyway. Are we talking about the same board?

>> The Ethernet clock is configured properly by
>> cpu_eth_init in ./arch/arm/cpu/arm926ejs/mx28/mx28.c. But later in the
>> boot process, board_eth_init in board/denx/m28evk/m28evk.c tries to
>> configure the Ethernet clock again. Unfortunately that second
>> configuration is just disabling the clock:
>> 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
>> 		CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
>> 		CLKCTRL_ENET_TIME_SEL_RMII_CLK);
>> After removing this line, I measured a 25MHz clock, communication with the
>> PHYs worked and I successfully tftp'ed a kernel from my server.
> 
> It's different -- M28EVK and MX28EVK are.

Yes, I know. I'm working with the MX28EVK, not the M28EVK.

>> Does you board have an external clock
>> oscillator for the PHYs?
> 
> Yes.

Aha, so we are talking about different boards.

>> If not, do you agree with removing this line?
> 
> No.

I'm sorry; I asked the wrong question. What I should have asked was: Do you agree
with not copying this line to the MX28EVK configuration?