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dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=05eRu5Hk5gKvbYa4WlKCEx0v3OIBRFb4f0ekRTzeEQI=; b=B7aoeHIJ0/9IOvDSlSqLsDS0gSa95aC9Fm4zxABcgW6D26Dcp/3RA5KtBZr+KJnH7kHFxXVzRprrwJiQIK4Xwl99UkMknw+kZ66qAZudrMuTXWG5chiCeyb+G8bix8XMHjpL+NCblK8AAwFFKHkmVP+gpwY5wY/mXnDSsGhsTg0= From: Bertrand Marquis To: Stefano Stabellini CC: "xen-devel@lists.xenproject.org" , Julien Grall , Volodymyr Babchuk Subject: Re: [PATCH v4 7/7] xen/arm: Sanitize CTR_EL0 Thread-Topic: [PATCH v4 7/7] xen/arm: Sanitize CTR_EL0 Thread-Index: AQHXqsPus1tQg1NxCEKJXP/MCMUVQ6unK+aAgACvBQA= Date: Fri, 17 Sep 2021 07:47:13 +0000 Message-ID: <2C65F110-1DC6-485F-AA4F-B4D5B40DAF8E@arm.com> References: <3a6a63701df71c0a0ea743c6229266077da0563e.1631772970.git.bertrand.marquis@arm.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3654.120.0.1.13) Authentication-Results-Original: kernel.org; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2021 07:47:21.1000 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe1de7d7-5469-4aa3-833b-08d979af6191 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT062.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3248 Hi Stefano, > On 16 Sep 2021, at 22:20, Stefano Stabellini wro= te: >=20 > On Thu, 16 Sep 2021, Bertrand Marquis wrote: >> Sanitize CTR_EL0 value between cores and taint Xen if incompatible >> values are found. >>=20 >> In the case of different i-cache types, the sanitize ctr_el0 will have a >> sanitize value but this is currently not used or exposed to guest which >> are seeing the original ctr_el0 value. >>=20 >> Use the opportunity to rename CTR_L1Ip to use an upper case name like >> Linux does. >> The patch is also defining ICACHE_POLICY_xxx instead of only having >> CTR_L1IP_xxx to sync the definitions with Linux and is updating the code >> using those accordingly (arm32 setup). >>=20 >> On platforms with only the same type of cores, this patch should not >> modify the current Xen behaviour. >>=20 >> Signed-off-by: Bertrand Marquis >> Signed-off-by: Stefano Stabellini >> --- >> Changes in v4: Remove TID2 support and handling of corresponding >> register emulation in vcpreg/vsysreg. >> Changes in v3: none >> Change in v2: Patch introduced in v2 >> --- >> xen/arch/arm/arm64/cpufeature.c | 6 ++---- >> xen/arch/arm/cpufeature.c | 2 ++ >> xen/arch/arm/setup.c | 2 +- >> xen/include/asm-arm/cpufeature.h | 9 +++++++++ >> xen/include/asm-arm/processor.h | 18 +++++++++++++++--- >> 5 files changed, 29 insertions(+), 8 deletions(-) >>=20 >> diff --git a/xen/arch/arm/arm64/cpufeature.c b/xen/arch/arm/arm64/cpufea= ture.c >> index d4679f5df3..6e5d30dc7b 100644 >> --- a/xen/arch/arm/arm64/cpufeature.c >> +++ b/xen/arch/arm/arm64/cpufeature.c >> @@ -275,9 +275,6 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[= ] =3D { >> ARM64_FTR_END, >> }; >>=20 >> -#if 0 >> -/* TODO: use this to sanitize the cache line size among cores */ >> - >> static const struct arm64_ftr_bits ftr_ctr[] =3D { >> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 *= / >> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, = 1, 1), >> @@ -294,7 +291,6 @@ static const struct arm64_ftr_bits ftr_ctr[] =3D { >> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SH= IFT, 4, 0), >> ARM64_FTR_END, >> }; >> -#endif >>=20 >> static const struct arm64_ftr_bits ftr_id_mmfr0[] =3D { >> S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNER= SHR_SHIFT, 4, 0xf), >> @@ -606,6 +602,8 @@ void update_system_features(const struct cpuinfo_arm= *new) >> */ >> SANITIZE_REG(dczid, 0, dczid); >>=20 >> + SANITIZE_REG(ctr, 0, ctr); >> + >> if ( cpu_feature64_has_el0_32(&system_cpuinfo) ) >> { >> SANITIZE_ID_REG(pfr32, 0, pfr0); >> diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c >> index 113f20f601..6e51f530a8 100644 >> --- a/xen/arch/arm/cpufeature.c >> +++ b/xen/arch/arm/cpufeature.c >> @@ -127,6 +127,8 @@ void identify_cpu(struct cpuinfo_arm *c) >>=20 >> c->dczid.bits[0] =3D READ_SYSREG(DCZID_EL0); >>=20 >> + c->ctr.bits[0] =3D READ_SYSREG(CTR_EL0); >> + >> aarch32_el0 =3D cpu_feature64_has_el0_32(c); >> #endif >>=20 >> diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c >> index 4ab13d0fbe..49dc90d198 100644 >> --- a/xen/arch/arm/setup.c >> +++ b/xen/arch/arm/setup.c >> @@ -650,7 +650,7 @@ static void __init setup_mm(void) >> panic("No memory bank\n"); >>=20 >> /* We only supports instruction caches implementing the IVIPT extens= ion. */ >> - if ( ((ctr >> CTR_L1Ip_SHIFT) & CTR_L1Ip_MASK) =3D=3D CTR_L1Ip_AIVI= VT ) >> + if ( ((ctr >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) =3D=3D ICACHE_POLICY= _AIVIVT ) >> panic("AIVIVT instruction cache not supported\n"); >>=20 >> init_pdx(); >> diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpuf= eature.h >> index 5219fd3bab..cab89ee142 100644 >> --- a/xen/include/asm-arm/cpufeature.h >> +++ b/xen/include/asm-arm/cpufeature.h >> @@ -267,6 +267,14 @@ struct cpuinfo_arm { >> register_t bits[1]; >> } dczid; >>=20 >> + /* >> + * CTR is only used to check for different cache types or policies = and >> + * taint Xen in this case >> + */ >> + struct { >> + register_t bits[1]; >> + } ctr; >> + >> #endif >>=20 >> /* >> @@ -339,6 +347,7 @@ extern struct cpuinfo_arm system_cpuinfo; >> extern void identify_cpu(struct cpuinfo_arm *); >>=20 >> #ifdef CONFIG_ARM_64 >> + >> extern void update_system_features(const struct cpuinfo_arm *); >> #else >> static inline void update_system_features(const struct cpuinfo_arm *cpui= nfo) >=20 > Spurious change. I fixed it on commit. Sorry for that and thanks. Bertrand >=20 > Reviewed-by: Stefano Stabellini