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([2601:646:c200:1ef2:80a8:9f3:92bf:a63f]) by smtp.gmail.com with ESMTPSA id k13sm14622746pfd.14.2020.05.25.10.19.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 May 2020 10:19:16 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Andy Lutomirski Mime-Version: 1.0 (1.0) Subject: Re: [RFC][PATCH 0/4] x86/entry: disallow #DB more Date: Mon, 25 May 2020 10:19:08 -0700 Message-Id: <2E6DBDE0-FEEA-467F-A380-4ED736B6C912@amacapital.net> References: <20200525110101.GG325303@hirez.programming.kicks-ass.net> Cc: Rasmus Villemoes , Andy Lutomirski , Thomas Gleixner , LKML , X86 ML In-Reply-To: <20200525110101.GG325303@hirez.programming.kicks-ass.net> To: Peter Zijlstra X-Mailer: iPhone Mail (17E262) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On May 25, 2020, at 4:01 AM, Peter Zijlstra wrote: >=20 > =EF=BB=BFOn Mon, May 25, 2020 at 12:40:38PM +0200, Peter Zijlstra wrote: >>> On Mon, May 25, 2020 at 12:02:48PM +0200, Rasmus Villemoes wrote: >>>=20 >>> Naive question: did you check disassembly to see whether gcc threw your >>> native_get_debugreg() away, given that the asm isn't volatile and the >>> result is not used for anything? Testing here only shows a "mov >>> %r9,%db7", but the read did seem to get thrown away. >>=20 >> Argh.. no I did not. Writing it all in asm gets me: >>=20 >> [ 1.627405] XXX: 3900 8304 22632 >>=20 >> which is a lot worse... >=20 > + u64 empty =3D 0, read =3D 0, write =3D 0, cpu =3D 0, cpu1 =3D 0; > + unsigned long dr7; > + > + for (i=3D0; i<100; i++) { > + u64 s; > + > + s =3D rdtsc(); > + asm volatile ("lfence; lfence;"); > + empty +=3D rdtsc() - s; > + > + s =3D rdtsc(); > + asm volatile ("lfence; mov %%db7, %0; lfence;" : "=3Dr" (dr7)); > + read +=3D rdtsc() - s; > + > + s =3D rdtsc(); > + asm volatile ("lfence; mov %0, %%db7; lfence;" :: "r" (dr7)); > + write +=3D rdtsc() - s; > + > + s =3D rdtsc(); > + asm volatile ("lfence; mov %0, %%db7; lfence;" :: "r" (dr7)); > + write +=3D rdtsc() - s; > + > + clflush(this_cpu_ptr(&cpu_dr7)); > + > + s =3D rdtsc(); > + asm volatile ("lfence;"); > + dr7 =3D this_cpu_read(cpu_dr7); > + asm volatile ("lfence;"); > + cpu +=3D rdtsc() - s; > + > + s =3D rdtsc(); > + asm volatile ("lfence;"); > + dr7 =3D this_cpu_read(cpu_dr7); > + asm volatile ("lfence;"); > + cpu1 +=3D rdtsc() - s; > + } > + > + printk("XXX: %ld %ld %ld %ld %ld\n", empty, read, write, cpu, cpu1); >=20 > [ 1.628252] XXX: 3820 8224 45516 35560 4800 >=20 > Which still seems to suggest using DR7 directly is probably a good > thing. It's slower than a L1 hit, but massively faster than a full miss. >=20 How about adding it to cpu_tlbstate? A lot of NMIs are going to read that a= nyway to check CR3. And blaming KVM is a bit misplaced. This isn=E2=80=99t KVM=E2=80=99s fault =E2= =80=94 it=E2=80=99s Intel=E2=80=99s. VT-x has two modes: DR access exits and= DR access doesn=E2=80=99t exit. There=E2=80=99s no shadow mode.