From: Ashutosh Dixit <ashutosh.dixit@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [Intel-gfx] [PATCH 5/8] drm/i915/gt: Add media RP0/RPn to per-gt sysfs
Date: Wed, 13 Apr 2022 11:11:06 -0700 [thread overview]
Message-ID: <2a11577139f82f50058a2167404b82fa7c80cb39.1649871650.git.ashutosh.dixit@intel.com> (raw)
In-Reply-To: <cover.1649871650.git.ashutosh.dixit@intel.com>
Retrieve RP0 and RPn freq for media IP from PCODE and display in per-gt
sysfs. This patch adds the following files to gt/gtN sysfs:
* media_RP0_freq_mhz
* media_RPn_freq_mhz
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Original-author: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 47 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++
2 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 2b1cd6a01724..2a3398003933 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -12,6 +12,7 @@
#include "i915_sysfs.h"
#include "intel_gt.h"
#include "intel_gt_regs.h"
+#include "intel_pcode.h"
#include "intel_gt_sysfs.h"
#include "intel_gt_sysfs_pm.h"
#include "intel_rc6.h"
@@ -669,13 +670,59 @@ static ssize_t media_freq_factor_store(struct device *dev,
return err ?: count;
}
+static ssize_t media_RP0_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ u32 val;
+ int err;
+
+ err = __intel_gt_pcode_read(gt, XEHPSDV_PCODE_FREQUENCY_CONFIG,
+ PCODE_MBOX_FC_SC_READ_FUSED_P0,
+ PCODE_MBOX_DOMAIN_MEDIAFF, &val);
+
+ if (err)
+ return err;
+
+ /* data_out - Fused P0 for domain ID in units of 50 MHz */
+ val *= GT_FREQUENCY_MULTIPLIER;
+
+ return sysfs_emit(buff, "%u\n", val);
+}
+
+static ssize_t media_RPn_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ u32 val;
+ int err;
+
+ err = __intel_gt_pcode_read(gt, XEHPSDV_PCODE_FREQUENCY_CONFIG,
+ PCODE_MBOX_FC_SC_READ_FUSED_PN,
+ PCODE_MBOX_DOMAIN_MEDIAFF, &val);
+
+ if (err)
+ return err;
+
+ /* data_out - Fused P0 for domain ID in units of 50 MHz */
+ val *= GT_FREQUENCY_MULTIPLIER;
+
+ return sysfs_emit(buff, "%u\n", val);
+}
+
static DEVICE_ATTR_RW(media_freq_factor);
static struct device_attribute dev_attr_media_freq_factor_scale =
__ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
+static DEVICE_ATTR_RO(media_RP0_freq_mhz);
+static DEVICE_ATTR_RO(media_RPn_freq_mhz);
static const struct attribute *media_perf_power_attrs[] = {
&dev_attr_media_freq_factor.attr,
&dev_attr_media_freq_factor_scale.attr,
+ &dev_attr_media_RP0_freq_mhz.attr,
+ &dev_attr_media_RPn_freq_mhz.attr,
NULL
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d5a4ecd374a..a45a776b2dae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6753,6 +6753,21 @@
#define DG1_UNCORE_GET_INIT_STATUS 0x0
#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
+#define XEHPSDV_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
+/* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
+#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/* XEHPSDV_PCODE_FREQUENCY_CONFIG param2 */
+#define PCODE_MBOX_DOMAIN_NONE 0x0
+#define PCODE_MBOX_DOMAIN_GT 0x1
+#define PCODE_MBOX_DOMAIN_HBM 0x2
+#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
+#define PCODE_MBOX_DOMAIN_MEDIA_SAMPLER 0x4
+#define PCODE_MBOX_DOMAIN_SYSTOLIC_ARRAY 0x5
+#define PCODE_MBOX_DOMAIN_CHIPLET 0x6
+#define PCODE_MBOX_DOMAIN_BASE_CHIPLET_LINK 0x7
+#define PCODE_MBOX_DOMAIN_BASE 0x8
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
--
2.34.1
next prev parent reply other threads:[~2022-04-13 18:11 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-13 18:11 [Intel-gfx] [PATCH 0/8] drm/i915: Media freq factor and per-gt enhancements/fixes Ashutosh Dixit
2022-04-13 18:11 ` [Intel-gfx] [PATCH 1/8] drm/i915: Introduce has_media_ratio_mode Ashutosh Dixit
2022-04-15 10:26 ` Rodrigo Vivi
2022-04-13 18:11 ` [Intel-gfx] [PATCH 2/8] drm/i915/gt: Add media freq factor to per-gt sysfs Ashutosh Dixit
2022-04-13 18:11 ` [Intel-gfx] [PATCH 3/8] drm/i915/pcode: Extend pcode functions for multiple gt's Ashutosh Dixit
2022-04-14 13:28 ` Jani Nikula
2022-04-14 22:31 ` Dixit, Ashutosh
2022-04-15 10:21 ` Rodrigo Vivi
2022-04-20 5:54 ` Dixit, Ashutosh
2022-04-20 16:32 ` Vivi, Rodrigo
2022-04-26 7:42 ` Jani Nikula
2022-04-13 18:11 ` [Intel-gfx] [PATCH 4/8] drm/i915/pcode: Add a couple of pcode helpers Ashutosh Dixit
2022-04-15 10:31 ` Rodrigo Vivi
2022-04-19 1:23 ` Dixit, Ashutosh
2022-04-13 18:11 ` Ashutosh Dixit [this message]
2022-04-25 9:39 ` [Intel-gfx] [PATCH 5/8] drm/i915/gt: Add media RP0/RPn to per-gt sysfs Kamil Konieczny
2022-04-26 0:43 ` Dixit, Ashutosh
2022-04-13 18:11 ` [Intel-gfx] [PATCH 6/8] drm/i915/gt: Fix memory leaks in " Ashutosh Dixit
2022-04-13 19:14 ` Dixit, Ashutosh
2022-04-13 18:11 ` [Intel-gfx] [PATCH 7/8] drm/i915/gt: Expose per-gt RPS defaults in sysfs Ashutosh Dixit
2022-04-13 18:11 ` [Intel-gfx] [PATCH 8/8] drm/i915/gt: Expose default value for media_freq_factor in per-gt sysfs Ashutosh Dixit
2022-04-14 0:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Media freq factor and per-gt enhancements/fixes Patchwork
2022-04-14 0:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-04-14 1:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-04-14 5:57 ` Dixit, Ashutosh
2022-04-14 7:11 ` Vudum, Lakshminarayana
2022-04-14 6:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-14 9:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-04-20 5:21 ` [Intel-gfx] [PATCH v2 0/9] " Ashutosh Dixit
2022-04-20 5:21 ` [Intel-gfx] [PATCH 1/9] drm/i915: Introduce has_media_ratio_mode Ashutosh Dixit
2022-04-20 5:21 ` [Intel-gfx] [PATCH 2/9] drm/i915/gt: Add media freq factor to per-gt sysfs Ashutosh Dixit
2022-04-21 20:57 ` Rodrigo Vivi
2022-04-26 0:29 ` Dixit, Ashutosh
2022-04-20 5:21 ` [Intel-gfx] [PATCH 3/9] drm/i915/pcode: Extend pcode functions for multiple gt's Ashutosh Dixit
2022-04-20 5:21 ` [Intel-gfx] [PATCH 4/9] drm/i915/gt: Convert callers to user per-gt pcode functions Ashutosh Dixit
2022-04-20 5:21 ` [Intel-gfx] [PATCH 5/9] drm/i915/pcode: Add a couple of pcode helpers Ashutosh Dixit
2022-04-20 5:21 ` [Intel-gfx] [PATCH 6/9] drm/i915/gt: Add media RP0/RPn to per-gt sysfs Ashutosh Dixit
2022-04-20 5:21 ` [Intel-gfx] [PATCH 7/9] drm/i915/gt: Fix memory leaks in " Ashutosh Dixit
2022-04-20 12:17 ` Andrzej Hajda
2022-04-20 16:12 ` Dixit, Ashutosh
2022-04-20 19:51 ` Andrzej Hajda
2022-04-24 22:36 ` Andi Shyti
2022-04-27 20:46 ` Dixit, Ashutosh
2022-04-28 14:36 ` Andrzej Hajda
2022-04-29 4:25 ` Dixit, Ashutosh
2022-05-02 6:22 ` Andrzej Hajda
2022-05-03 4:29 ` Dixit, Ashutosh
2022-04-20 5:21 ` [Intel-gfx] [PATCH 8/9] drm/i915/gt: Expose per-gt RPS defaults in sysfs Ashutosh Dixit
2022-04-20 5:21 ` [Intel-gfx] [PATCH 9/9] drm/i915/gt: Expose default value for media_freq_factor in per-gt sysfs Ashutosh Dixit
2022-04-20 6:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Media freq factor and per-gt enhancements/fixes Patchwork
2022-04-29 19:56 [Intel-gfx] [PATCH v4 0/8] " Ashutosh Dixit
2022-04-29 19:56 ` [Intel-gfx] [PATCH 5/8] drm/i915/gt: Add media RP0/RPn to per-gt sysfs Ashutosh Dixit
2022-05-10 7:37 ` Tvrtko Ursulin
2022-05-12 4:25 ` Dixit, Ashutosh
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