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Tue, 26 Mar 2024 10:00:56 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::31a1:93ed:8501:f2c9]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::31a1:93ed:8501:f2c9%3]) with mapi id 15.20.7409.031; Tue, 26 Mar 2024 10:00:56 +0000 Message-ID: <2a35ee1b-4ef4-49e2-a481-d6929e522f16@intel.com> Date: Tue, 26 Mar 2024 15:30:49 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/11] drm/i915/dp: Fix DSC line buffer depth programming To: Imre Deak , CC: References: <20240320201152.3487892-1-imre.deak@intel.com> <20240320201152.3487892-2-imre.deak@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20240320201152.3487892-2-imre.deak@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: BMXP287CA0021.INDP287.PROD.OUTLOOK.COM (2603:1096:b00:2c::25) To DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5341:EE_|DM4PR11MB7303:EE_ X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This is limited both > by the source's and sink's maximum line buffer depth, but the former one > was not taken into account. On all Intel platform's the source's maximum > buffer depth is 13, so the overall limit is simply the minimum of the > source/sink's limit, regardless of the DSC version. > > This leaves the DSI DSC line buffer depth calculation as-is, trusting > VBT. > > On DSC version 1.2 for sinks reporting a maximum line buffer depth of 16 > the line buffer depth was incorrectly programmed as 0, leading to a > corruption in color gradients / lines on the decompressed screen image. > > Cc: dri-devel@lists.freedesktop.org > Signed-off-by: Imre Deak LGTM. Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++---------- > include/drm/display/drm_dsc.h | 3 --- > 2 files changed, 6 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index af7ca00e9bc0a..dbe65651bf277 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -89,6 +89,9 @@ > #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 > #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 > > +/* Max DSC line buffer depth supported by HW. */ > +#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 > + > /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ > #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 > > @@ -1703,7 +1706,6 @@ static int intel_dp_dsc_compute_params(const struct intel_connector *connector, > { > struct drm_i915_private *i915 = to_i915(connector->base.dev); > struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > - u8 line_buf_depth; > int ret; > > /* > @@ -1732,20 +1734,14 @@ static int intel_dp_dsc_compute_params(const struct intel_connector *connector, > connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & > DP_DSC_RGB; > > - line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd); > - if (!line_buf_depth) { > + vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, > + drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); > + if (!vdsc_cfg->line_buf_depth) { > drm_dbg_kms(&i915->drm, > "DSC Sink Line Buffer Depth invalid\n"); > return -EINVAL; > } > > - if (vdsc_cfg->dsc_version_minor == 2) > - vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? > - DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; > - else > - vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? > - DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; > - > vdsc_cfg->block_pred_enable = > connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & > DP_DSC_BLK_PREDICTION_IS_SUPPORTED; > diff --git a/include/drm/display/drm_dsc.h b/include/drm/display/drm_dsc.h > index bc90273d06a62..bbbe7438473d3 100644 > --- a/include/drm/display/drm_dsc.h > +++ b/include/drm/display/drm_dsc.h > @@ -40,9 +40,6 @@ > #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 > #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 > #define DSC_PPS_NATIVE_420_SHIFT 1 > -#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 > -#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 > -#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 > > /** > * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters