From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=45121 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PJNhT-0007Xb-2w for qemu-devel@nongnu.org; Fri, 19 Nov 2010 04:56:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PJNhQ-0004Sr-LI for qemu-devel@nongnu.org; Fri, 19 Nov 2010 04:56:10 -0500 Received: from mail.valinux.co.jp ([210.128.90.3]:52287) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PJNhQ-0004SZ-Bd for qemu-devel@nongnu.org; Fri, 19 Nov 2010 04:56:08 -0500 From: Isaku Yamahata Date: Fri, 19 Nov 2010 18:56:03 +0900 Message-Id: <2a4a27e9b27f0e75052fc52f36449e397fd5a65d.1290160397.git.yamahata@valinux.co.jp> In-Reply-To: References: In-Reply-To: References: Subject: [Qemu-devel] [PATCH v2 6/6] pci bridge: implement secondary bus reset List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: skandasa@cisco.com, Anthony Liguori , etmartin@cisco.com, wexu2@cisco.com, mst@redhat.com, yamahata@valinux.co.jp, pbonzini@redhat.com Emulates secondary bus reset when secondary bus reset bit is written from 0 to 1. Signed-off-by: Isaku Yamahata Signed-off-by: Anthony Liguori --- hw/pci_bridge.c | 12 +++++++++++- 1 files changed, 11 insertions(+), 1 deletions(-) diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c index 58cc2e4..618a81e 100644 --- a/hw/pci_bridge.c +++ b/hw/pci_bridge.c @@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) void pci_bridge_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { + PCIBridge *s = container_of(d, PCIBridge, dev); + uint16_t bridge_control = pci_get_word(d->config + PCI_BRIDGE_CONTROL); + uint16_t bridge_control_new; + pci_default_write_config(d, address, val, len); if (/* io base/limit */ @@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d, /* memory base/limit, prefetchable base/limit and io base/limit upper 16 */ ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { - PCIBridge *s = container_of(d, PCIBridge, dev); pci_bridge_update_mappings(&s->sec_bus); } + + bridge_control_new = pci_get_word(d->config + PCI_BRIDGE_CONTROL); + if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) && + (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) { + /* 0 -> 1 */ + pci_bus_reset(&s->sec_bus); + } } void pci_bridge_disable_base_limit(PCIDevice *dev) -- 1.7.1.1