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Mon, 28 Jun 2021 08:17:08 -0700 (PDT) Received: from [192.168.1.11] ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id co18sm20349164pjb.37.2021.06.28.08.17.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Jun 2021 08:17:08 -0700 (PDT) Subject: Re: [PATCH 02/18] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210628135835.6690-1-peter.maydell@linaro.org> <20210628135835.6690-3-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <2a6d7c6b-784c-49e2-a390-538c0dcd0514@linaro.org> Date: Mon, 28 Jun 2021 08:17:06 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210628135835.6690-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/28/21 6:58 AM, Peter Maydell wrote: > The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH > insns had some bugs: > * the 32x32 multiply of elements was being done as 32x32->32, > not 32x32->64 > * we were incorrectly maintaining the accumulator in its full > 72-bit form across all 4 beats of the insn; in the pseudocode > it is squashed back into the 64 bits of the RdaHi:RdaLo > registers after each beat > > In particular, fixing the second of these allows us to recast > the implementation to avoid 128-bit arithmetic entirely. > > Since the element size here is always 4, we can also drop the > parameterization of ESIZE to make the code a little more readable. > > Suggested-by: Richard Henderson > Signed-off-by: Peter Maydell > --- > Richard suggested this change in review of v1 of the original > MVE-slice-1 series, but at that time I was incorrectly reading the > pseudocode as requiring the 72-bit accumulation over all four beats. > Testing with a wider range of inputs showed I was wrong... > --- > target/arm/mve_helper.c | 38 +++++++++++++++++++++----------------- > 1 file changed, 21 insertions(+), 17 deletions(-) Reviewed-by: Richard Henderson r~